vhdl考試時(shí)鐘

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1、HI vhdl考試時(shí)鐘 實(shí) 驗(yàn) 報(bào) 告 應(yīng)用技術(shù)一班 朱曉園，汪仙仙，張明星，胡亞洲 一:分頻模塊 定義elk為時(shí)鐘輸入引腳。輸入20MHZ的頻率。定義一個(gè)clklhz 分須和ckllOOHZ分頻。 LIBRARY ieee; USE i eee. std_Iog i c_1164. a 11; USE ieee. std_logic_arith. all; USE i eee. std_Iog i c_uns i gned. all; ENTITY FENPIN IS PORT ( elk : IN STD LOGIC； oclk : OUT

2、 STD LOGIC; ocIk1OOhz : OUT STD_LOGIC )； END FENPIN; ARCH ITECTURE FENPIN .architecture OF FENPIN IS BEGIN process(elk) variable ent :integer range 0 to 20000000; begin if rising_edge(cIk) then ent:=cnt+1; if cnt<=10000000 then oclk<='「； else if cnt<=20000000 then cnt:=0； oelkV'O'; e

3、nd if; end if; end if; end process; process(elk) variable cnt1 :integer range 0 to 20000000; begin if rising_edge(cIk) then if cnt1<=200000 then cnt1:=0; oclk100hz<='r； else cnt1 :=cnt1+1; oclk100hz<='0,; end if; end if; end process; END FENPIN architecture; 二：按鍵消抖 因?yàn)闄C(jī)械鍵盤(pán)存在抖動(dòng)現(xiàn)象，所以

4、需要用延時(shí)，軟件去抖。這里 用100HZ的頻率，一旦出現(xiàn)低電平，就計(jì)數(shù)10次，一共100MS, 然后再次檢測(cè)，如果仍為低，就輸出0信號(hào)。 LIBRARY ieee; USE i eee.std_Iog i c_1164. a I I; USE ieee.std_logic_arith. all; USE ieee. std_ I ogi consigned, all; ENT ITY XIAODOU IS PORT ( elk : IN STD LOGIC; rst_key : IN STD_LOGIC; set_key : IN STD_LOGIC; position

5、: IN STD_LOGIC; addup : IN STD_LOGIC; position_s : IN STD_LOGIC; addup_time : IN STD_LOGIC; rst^time : OUT STD_LOGIC; set_t i me : OUT STD_LOGIC ); END XIAODOU; ARCH ITECTURE XIAODOU_architecture OF XIAODOU IS s i gnaI cnt:std_logic_vector (3 downto 0); BEGIN process (elk) begin if risin

6、g_edge(cIk) then if rst_key=,1'then cnt<=n0000n; rst time<=,1'; else if cnt="1001" then rst time<=,0,; cnt<=cnt; else cnt<=cnt+1; rst_time<='1'; end if; end if; end if; end process; END XIAODOU architecture; 三：按鍵處理信號(hào) set鍵用來(lái)檢測(cè)設(shè)置按鍵，第一次按下，為設(shè)置，第二次按下， 為取消按鍵。position為位置選擇，按下一次選擇第一個(gè)，按下二次 為

7、第二次，以此類(lèi)推。其余按鍵正常輸出。 LIBRARY ieee; USE i eee. std_Iog i c_1164. a I I; USE ieee. std_logic_arith. all; USE ieee. std_ I ogi consigned, all; ENT ITY ANJIANCHULI IS PORT ( elk : IN STD LOGIC; rst : IN STD LOGIC; set : IN STD LOGIC; add : IN STD LOGIC; position : IN STD_LOGIC; set out : OUT

8、STD LOGIC; rst out : OUT STD LOGIC; add out : OUT STD LOGIC; positionl : OUT STD_LOGIC; position2 : OUT STD.LOGIC; positions : OUT STD_LOGIC; pos i t i on4 : OUT STD_LOGIC )； END ANJIANCHULI; ARCHITECTURE ANJIANCHULI_arch i tecture OF ANJIANCHULI IS signaI ent: std_Iogic_vector(1 downto 0);

9、 signaI cnt1: std_Iogic_vector(1 downto 0); begin process (set) begin if set'event and set=l0,then cnt<=cnt+1; end if; end process; set_out<='0'when ent (0)=,0' else'1'when ent (0)=,0, else'O'; process (position) begin if position'event and position =,0fthen cnt1<=cnt1+1; end if; case

10、 cnt1 is when n00n=>position1<=,0,;position2<='1 *;position3<=,11;positio n4<=T; when "01n=>pos i t i on1<='11;pos i t i on2<='0';pos i t i on3<=,1';pos i t i o n4<='1'; when "10n=>position1<=,11;position2<=<11;pos i t i on3<='01;positio n4<='1'; when "11n=>position1<=,11;position2<='1'；pos

11、ition3<='1';positio n4<=,0,; when others=>nulI; end case; end process; process (elk) begin if rising_edge(cIk)then rst out<=rst: add out<=add: end if; end process; END ANJIANGHULI architecture; 四：計(jì)數(shù)十 十進(jìn)制計(jì)數(shù)為時(shí)鐘個(gè)位計(jì)數(shù)，自動(dòng)計(jì)數(shù)滿10, CY進(jìn)1給六進(jìn)制 模塊。手動(dòng)設(shè)置時(shí)，不進(jìn)位 LIBRARY ieee; USE ieee. std_Iogic_1164. al

12、I; USE i eee. std_Iog i c_ar i th. a 11; USE ieee. std_Iogic_unsigned. all; ENT ITY JI SHUSH I IS PORT ( elk : IN STD LOGIC; rst : IN STD LOGIC; set : IN STD LOGIC; add : IN STD LOGIC; position : IN STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR(3 downto 0)； os : OUT STD LOGIC ); END JI SHU

13、SH I vhd; ARCHITECTURE JI SHUSH I_vhd_arch i tecture OF JISHUSHI_vhd IS signaI buffer_os:std_logic; s i gnaI adder_buffer:std_logic_vector(3 downto 0); signaI add_cnt:std_Iogic_vector(3 downto 0); BEGIN buffer_os<='O' when set='0' else elk; process (set, posit ion, buffer_os) begin if rst=,

14、01 then adder buffer<=n0000"； elsif set='O' and position='O' then adder_buffer<=add_cnt; elsif rising_edge(buffer_os) then if adder_buffer=n100111 then adder buffer<=n0000"； os<='r； else adder buffer<=adder buffer+1; os<='0'; end if; end if; end process; dataout<=adder buffer; process

15、 (add) begin if add1 event and add='O' then if add_cnt=H1OO1n then add cnt<="0000n; else add cnt<=add cnt+1: end if; end if; end process; END JI SHUSH I vhd architecture; 五：計(jì)數(shù)六 六進(jìn)制計(jì)數(shù)為時(shí)鐘個(gè)位計(jì)數(shù)，自動(dòng)計(jì)數(shù)滿5, CY進(jìn)1給十進(jìn)制模塊。 手動(dòng)設(shè)置時(shí)，不進(jìn)位 LIBRARY ieee; USE ieee.std_Iogic_1164. al I; USE i eee. std_Iog i

16、 c_ar i th. a 11; USE ieee. std_ I ogi consigned, all; ENT ITY JISHULIU_vhd IS PORT ( elk : IN STD LOGIC; set ： IN STD LOGIC; add : IN STD LOGIC; position : IN STD.LOGIC; rst : IN STD LOGIC; dataout : OUT STD_LOGIC_VECTOR(3 downto 0); os ： OUT STD.LOGIC )； END JISHULIU vhd; ARCHITECTUR

17、E JISHULIU_vhd_archi tecture OF JISHULIU_vhd IS signaI buffer_os :std_logic; s i gnaI adder_buffer :std_logic_vector (3 downto 0); s i gnaI add_cnt: std_Iog i c_vector (3 downto 0); BEGIN buffer_os<='0' when set=10, else elk; process(buffer_os, rst, set, position) begin if rst=1O, then adder

18、 buffer<=MOOOOn; elsif set=,O' and position<=*O' then adde r_buffe r<=add_cnt; elsif rising_edge(buffer_os) then if adder_buffer=,,0101" then adder buffer<=n0000n; os<='r； else adder_buffer<=adder_buffer+1; os<=,0"; end if; end if; end process; dataout<=adder_buffer; process(add) begin

19、 if add 1 event and add='O' then if add_cnt="0101" then add cnt<="0000n; else add cnt<=add cnt+1; end if; end if; end process; END JISHULIU vhd architecture; 六：譯碼 LIBRARY ieee； USE i eee.std_Iog i c_1164. a I I; USE i eee. std_Iog i c_ar i th. a 11; USE ieee. std_Iogic_unsigned. all;

20、ENT ITY code_moduIe IS —{{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( data in : IN STD_LOGIC_VECTOR (3 downto 0); dataout : OUT STD_LOGIC_VECT0R(6 downto 0) )； END code module: ARCH ITECTURE code moduIe architecture OF code moduIe IS BEGIN process (data i n) begin case datain is whe

21、n ,,0000,,=>dataout<="0000001,f； when "0001"=>dataout<="1001111"; when n0010"=>dataout<=n0010010"; when "0011n=>dataout<="0000110"; when "0100n=>dataout<=n1001100"； when n0101n=>dataout<='f0100100n； when “0110” =>dataout<="0100000”； when "0111"=>dataout<="0001111"; when n1000n =>dataout<=n00

22、00000"； when ”1001n=>dataout<=H0000100n； when others=>nulI; end case; end process; END code module architecture; 七：閃爍 當(dāng)position為0時(shí)，讓此數(shù)碼管閃爍，當(dāng)set和position都為1 時(shí)，正常顯示。 LIBRARY ieee; USE ieee.std_Iogic_1164. all; USE ieee. std_logic_ar ith. all; USE ieee. std_logic_unsigned. al I; ENTITY FLAS

23、H_vhd IS PORT ( elk : IN STD_LOGIC; cIk_syn : IN STD_LOGIC; set ： IN STD LOGIC; position : IN STD_LOGIC; data in : IN STD_LOGIC_VECTOR(6 downto 0); dataout : OUT STD_LOGIC_VECTOR(6 downto 0) )； END FLASH_vhd; ARCHITECTURE FLASH_vhd .architecture OF FLASH.vhd IS begin process (set, pos i t i on, c I k) begin if rising_edge(cIk_syn) then if set='O' and position='0' then if clk=T then dataout<=datain; else dataout<="1111111,,; end if; else dataout <= data in; end if; end if; end process; END FLASH vhd architecture;