基于PLC的分料自動機控制系統(tǒng)設(shè)計【分料自動機PLC控制系統(tǒng)設(shè)計】
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編號
無錫太湖學(xué)院
畢業(yè)設(shè)計（論文）
相關(guān)資料
題目： 汽車自動清洗機PLC控制系統(tǒng)設(shè)計
信機 系 機械工程及自動化專業(yè)
學(xué) 號：
學(xué)生姓名：
指導(dǎo)教師： （職稱：副教授 ）
（職稱： ）
2013年5月25日
目 錄
一、畢業(yè)設(shè)計（論文）開題報告
二、畢業(yè)設(shè)計（論文）外文資料翻譯及原文
三、學(xué)生“畢業(yè)論文（論文）計劃、進度、檢查及落實表”
四、實習(xí)鑒定表
無錫太湖學(xué)院
畢業(yè)設(shè)計（論文）
開題報告
題目： 汽車自動清洗機PLC控制
系統(tǒng)設(shè)計
信機 系 機械工程及自動化 專業(yè)
學(xué) 號：
學(xué)生姓名：
指導(dǎo)教師： （職稱：副教授 ）
（職稱： ）
2012年11月25日
課題來源
自擬
科學(xué)依據(jù)（包括課題的科學(xué)意義；國內(nèi)外研究概況、水平和發(fā)展趨勢；應(yīng)用前景等）
（1） 課題科學(xué)意義
隨著我國汽車保有量的持續(xù)增加，汽車清洗作為汽車保養(yǎng)的一個前提工序，就顯得越來越重要。開發(fā)汽車自動清洗機對于節(jié)約水資源和環(huán)境保護，提高勞動生產(chǎn)率具有重要意思。本課題屬工程設(shè)計類課題，要求完成汽車自動清洗機的PLC控制系統(tǒng)設(shè)計。通過本設(shè)計，可以幫助學(xué)生加深對本專業(yè)的相關(guān)知識理解和提高綜合運用專業(yè)知識能力
（2） 汽車自動清洗機研究概況
汽車清洗是近兒年才在我國逐漸發(fā)展起來的新興行業(yè)，具備資金和技術(shù)門檻低的特點。由于從國家到地方，相關(guān)的行業(yè)標(biāo)準(zhǔn)不是十分完備，對場地、環(huán)保、設(shè)備、技術(shù)、經(jīng)營管理等方面都缺乏明確的規(guī)定和要求，導(dǎo)致本應(yīng)被淘汰地洗車方式仍然在洗車市場上大行其道，而無水洗車、全白動電腦機械化洗車等先進的洗車方式卻在市場份額中占有很小的比例。在歐、美等發(fā)達國家，經(jīng)過多年的發(fā)展，科學(xué)洗車的理念己深入人心，洗車市場的洗車方式有全自動電腦洗車機洗車、燕汽洗車和無水洗車，其中尤以全自動電腦洗車為主。在我國建設(shè)、美化城市，創(chuàng)建現(xiàn)代化城市的發(fā)展土題中，在全社會節(jié)約水資源、保護環(huán)境、可持續(xù)發(fā)展的潮流中，追求時尚、效率和環(huán)保已成為汽車美容服務(wù)行業(yè)的重要內(nèi)容和發(fā)展方向。目前，城市落后的人工洗車方式己不能適應(yīng)現(xiàn)代化城市的市容衛(wèi)生和行業(yè)發(fā)展的需求，也不符合企業(yè)的規(guī)模經(jīng)營、專業(yè)化、規(guī)范化的要求，更談不上行業(yè)的可持續(xù)發(fā)展。要想中國的洗車行業(yè)健康有序地發(fā)展，當(dāng)務(wù)之急，必須推廣科學(xué)的、環(huán)保的、符合中國國情的科學(xué)洗車方式，要用新的理念、新的思路和新的方法來管理洗車行業(yè)，提升行業(yè)的形象和競爭力。
全自動電腦洗車機，順應(yīng)時代的需要應(yīng)運而生。它的出現(xiàn)是向傳統(tǒng)洗車方式的挑戰(zhàn)，必將引起洗車行業(yè)市場一場激烈的竟?fàn)幒蛶砀拘缘淖兏铩Ｖ袊南窜囆袠I(yè)要發(fā)展，必須與國際洗車業(yè)接軌，縮小與國際先進洗車行業(yè)的差距。因此，推廣和應(yīng)用全自動洗車機勢在必行。
研究內(nèi)容
（1） 了解汽車自動清洗機的工作原理，國內(nèi)外的研究發(fā)展現(xiàn)狀；
（2） 完成汽車自動清洗機控制系統(tǒng)設(shè)計；
?全白動洗車機的總體方案設(shè)計
?全自動洗車機電氣控制系統(tǒng)設(shè)計
?全自動洗車機PLC控制系統(tǒng)軟件設(shè)計
（3） 完成有關(guān)工藝流程設(shè)計、控制系統(tǒng)主電路、控制電路和電氣元件的選型設(shè)計。
（4） 熟練掌握有關(guān)計算機繪圖軟件，并繪制有關(guān)電路圖紙，編制PLC控制程序；
完成設(shè)計說明書的撰寫，并翻譯外文資料1篇。
擬采取的研究方法、技術(shù)路線、實驗方案及可行性分析
通過對汽車清洗機功能要求和運行過程的分析，確定汽車清洗機的總體設(shè)計方案，對水循環(huán)處理系統(tǒng)進行設(shè)計。并主要進行汽車清洗機驅(qū)動和控制系統(tǒng)的設(shè)計。針對汽車清洗機的特點，采用電力和氣壓驅(qū)動兩種驅(qū)動方式，為后續(xù)精密控制頂刷、側(cè)刷和吹干系統(tǒng)的運行滿足仿形要求創(chuàng)造了條件。在控制部分，應(yīng)用傳感器和可編程序控制器技術(shù)，對汽車清洗機PLC控制系統(tǒng)進行了硬件設(shè)計和控制軟件編程。
研究計劃及預(yù)期成果
研究計劃：
2012年11月12日-2012年12月2日：按照任務(wù)書要求查閱論文相關(guān)參考資料，填寫畢業(yè)設(shè)計開題報告書
2012年12月3日-2013年1月20日：進入工廠實習(xí)，了解企業(yè)生產(chǎn)流程。
2013年2月11日-2月16日：查找一篇關(guān)于PLC的的英文資料，并完成翻譯。
2013年2月18日-3月9日：確定汽車自動清洗機的總體方案以及主電路圖。
2013年3月11日-3月16日：電路中電動機選型。
2013年3月18日-2013年3月30日：確定I/O地址分配及接線圖。
2013年4月1日-2013年4月13日：完成PLC的選型以及編寫梯形圖。
2013年4月15日-2013年5月10日：撰寫論文和相關(guān)資料。
2013年5月13日-2013年5月25日：完成論文，準(zhǔn)備答辯。
預(yù)期成果：
按照計劃完成本課題的設(shè)計，可以基本實現(xiàn)汽車自動清洗機的工作要求。所設(shè)計的控制程序，能夠基本實現(xiàn)。
特色或創(chuàng)新之處
（1）主題明確，有針對性，安全，效率高，通用性強。
（2）使用簡易，功能完善，成本較低。
已具備的條件和尚需解決的問題
條件：PLC控制的基礎(chǔ)知識，與課題相關(guān)的資料、期刊、文摘等
問題：PLC的編程軟件及一些汽車清洗機方面的知識
指導(dǎo)教師意見
指導(dǎo)教師簽名：
年 月 日
教研室（學(xué)科組、研究所）意見
教研室主任簽名：
年 月 日
系意見
主管領(lǐng)導(dǎo)簽名：
年 月 日
英文原文
Journal of Software Engineering and Applications, 2011, 4, 172-180
doi:10.4236/jsea.2011.43019 Published Online March 2011 (http://www.SciRP.org/journal/jsea)
Development of Equivalent Virtual Instruments to PLC Functions and Networks
Mohammad A. K. Alia, Tariq M. Younes, Mohammad Abu Zalata
Mechatroncis Engineering Department, Faculty of Engineering Technology, Al-Balqa Applied University, Amman, Jordan.
Email: makalalia2000@yahoo.com, tariqmog@hotmail.com, abuzalata@yahoo.com
Received February 20th, 2011; revised March 5th, 2011; accepted March 10th, 2011.
ABSTRACT
This research is a continuation to our work which was published in [1]. Eight different timing VIs are designed and tested. These include ON-Delay, OFF-Delay, Single Shot, Retriggerable Monostable, and Accumulative software-based timers. Using hardware programmable counter/timer chip (DAQ-STC-24bit) and PCI MIO-16E-1 DAQ board, another two precise timers are designed. At the end of the paper, for illustration purposes, an electro-pneumatic drive system was developed and controlled utilizing designed on-delay timers VI functions. Results of experiment show complete coincidence between the PLC-based control and Virtual PLC-based program results.
Keywords: PLC, Virtual PLC, LabVIEW, Programmable Timers
1. Introduction
In our work “Design of a virtual PLC using LabVIEW” we have shown how it is possible to create LabVIEW VIs which represent PLC functions and networks. We compared between PC-based and PLC-based control systems, and came to the fact that both systems are continuously developing in the same direction in order to obtain better programmability, connectivity and communication interfacing. At the time being the PC-based DCSs are suited for industrial applications. They are robust and they easily work in an open architecture mode, while PLCs are equipped with specific MMI software and pseudo-standard commutation software also. We have shown that in order to improve the programmability of PACs, we practically brought the PLC to the computer utilizing by that numerous advantages of computers such as multitasking, unlimited memory, high speed and the possibility of creating unlimited number of programmable objects such as counters, timers, shift registers and others. Because of the limited size of previous work, we were not able to cover other important VIs which may be used also as the analog of PLC functions. In this paper we shall develop different types of programmable timers using LabVIEW software [2] and NI DAQ board hardware also. The LabVIEW basic functions that provide timing on millisecond level are the “wait” and “wait for Next ms Multiple” VIs. Both are based on the same under lying mechanism. Most applications work comfortably with available LabVIEW measurements that resolve milliseconds, and many more operate with second resolution[3-4]. A few applications demand sub-millisecond resolution and response time, which is problematic due primarily to operating system and not a LabVIEW limitation[5]. If the application requires higher accuracy or resolution than the built-in timing functions can supply, then one will have to use some additional hardware, such as NI-DAQ boards or an external clock [6]. NI-boards have two 24bit counter chips and several on-board clocks that can be counted to produce accurate timing (intervals). With the DAQ counter-timer VIs, one can configure the on-board versatile hardware for a variety of tasks including the accurate generation of timed pulses, counting events, and the measurement of periods and frequencies. The counter output generates a pulse when a preprogrammed terminal count (TC) is reached. The pulse may be used for sequencing purposes. Similar hardware-based timing may be performed using windows API function “Query performance counter”. This function looks at a high resolution system hardware counter that runs at approximately 1.2 MHz or 0.8 microsecond count. The actual resolution, once we account for the delay in calling the function, will be considerably less, but still far better than one millisecond. Concerning Real-Time operating systems (RTOS), they are designed to run a single program with very precise timing. They can allow to run loops with nearly the same thing each iteration (typically within microseconds). Timing for hard RTOSs can be performed using the DAQ card’s internal clock, giving better accuracy than software timing functions [7]. At the time being, some hardware platforms feature an on-board FPGA, that may be programmed using LabVIEW FPGA module. NI ComactRIO and single-board RIO are examples. The default clock rate of LabVIEW FPGA is 40 MHz. General FPGA timing VIs [2] may generate one clock period. One-shot pulse or measure the period, pulse width, accumulate period over a specified number of pulses and count pulses over a specified period of time. Nevertheless FPGA VIs do not include ready On-delay timers, OFF-delay timers and momostable retriggerable timers which find extensive applications in PLC sequential control programs. Building on the above, the target of this work is to illustrate the design of different types of timing VIs using LabVIEW software in order to be used as programming elements in virtual PLC programs.
2. ON-Delay Timer
1) ON-Delay Timer-1
Figure 1 shows the front panel and the block diagram components of a software-based ON-Delay Timer. The loop iteration is indicated in seconds. Because the loop iteration starts from zero, the increment function is added in order to start it at one. Since the wait icon has 100 ms delay between every two iterations a factor of 10 is multiplied by timer preassigned value, in order to measure the time delay in seconds. After the application of enable signal it takes some delay time interval for the equal function to have a true state at the output. If the input signal is disabled, the timer output instantly changes to low state.
2) ON-Delay Timer-2
The components of the VI are shown in the block diagram, Figure 2. Initially the input signal is not enabled and the false case is activated. The output of select icon will be zero, which is lower than the timer preset value, and as a result of that the output of the timer is OFF. When the input signal is enabled the true case is executed and the select icon will output the value that comes form the output of the case structure. The initial value of the iteration local variable is zero, then it will be incremented after a delay caused by the wait icon, and then compared by timer preset value. When the output of the comparison function is true, the output of the timer becomes high. When the enable input signal becomes low, the output of the timer becomes low simultaneously. In this VI, the checking of the case structure is continuous at a scan rate equal to one millisecond, which is accepted for many applications.
（a）
（b）
(c)
Figure 1. On-delay timer-1, (a) The Block Diagram; (b) The Front Panel; (c) Subicon
3. OFF-Delay Time
1) OFF-Delay Timer-1
The front panel and block diagram are shown in Figure3. The while loop and other VI components are located inside the false case of the case structure. The true case has a local variable of the timer output, which is wired to the selector terminal. The enable input signal is connected to the selector terminal of the false case.
2) OFF-Delay Timer-2
The block diagram is given in Figure 4. When the input is enabled the true case is activated and the select icon will be selected to zero. In this case the output of the comparison function is false and the timer output is true. When the input signal is disabled the false case executes, and the select icon is selected to the value that comes from the output of the case structure. When the off-delay time interval elapses the output of the comparison function is true and the timer output is false.
(a)
(b)
Figure 4. OFF delay timer 4, (a) True case; (b) False case
4. Single-Shot Timer
The block diagram and front panel are shown in Figure 5. The Boolean indicator prevents the timer output to turn ON again after the elapse of the preset value of one-shot timer. During the false case the output is OFF, and during the comparison time the timer output enabled high. At the end of comparison the timer output is low again.
5. Retriggerable Monostable Timer VI
Figure 6 shows the block diagram and the front panel of this timer. When the enable input switches ON, the timer output immediately turns ON and the timer starts timing. As soon as the preset time value has elapsed, the timer output switches OFF, even if the enable input is still ON. Every OFF to ON transition of the enable input resets the timer, i.e. the elapsed time is set to pre-set value and timer output is switched ON. Figure 7 shows a three mode delay timer. ON delay, OFF delay and Retriggerable Monostable timers are built in one block diagram, where the programmer can select the required timer mode.
6. Accumulative Timer–VI
The timer block diagram and front panel are shown in Figure 8. The output of the add function and the timer preset value are connected to the equal comparison function. The output equal comparison function is connected to one terminal of the OR gate. The other input of the OR gate function is connected to the inverted input signal. The output of OR function is connected to conditional terminal of the while loop.
(a)
(b)
(c)
Figure 3. OFF-delay timer, (a) The block diagram; (b) The front panel; (c) Subicon.
The conditional terminal is connected to one terminal of the AND gate. The other input of the AND gate is connected to local variable of the input signal. The output of the AND gate is the timer output. The while loop and above mentioned components are inside the true case of the case structure. When the input signal is not enabled the false case is activated, then the local variable of accumulative indicator has a zero value and that value will be stored in the current time indicator. The true case will be activated when the input signal is enabled. If the input signal is disabled before the equal comparison function is true, the false case is activated and the local variable of the loop iteration has that value at which the loop was stopped and this value will be stored in the current time indicator. If the input signal is activated again, the true case is activated and the previous operation is repeated again, where the loop iteration is added to the previous value, which is stored in the current timer indictor, then it is compared with the timer preset value. The process of enabling and displaying the input signal continues until the output of the equal comparison function becomes true and as a result the timer output turns ON. Figure 9 shows a designed VI in order to measure time interval in the range of nanoseconds. A hardware programmable counter/timer chip (DAQSTC-24 bit )and a hardware time base signal source located on PCI-MIO-16E-1 DAQ-Board are utilized. The program is built using the advance subVIs because they are more flexible than the easy VIs or intermediate VIs. A closely related issue is the use of two hardware counters for measurement of sampling time interval. In such a case the signal of interest is fed to a counter source terminal and to the gate terminal of another counter. The source terminal of the second counter is fed by a periodic clock signal with a much higher frequency than the expected sampling frequency. Normally, the internal time base of the counter provides more than adequate source to count (i.e. 20 MHZ and above). To receive an accurate indication of the time, both counters must start at the same instant. By diving the count of the second counter by the frequency we find the time. As an example, we shall consider an electro-pneumatic drive system. The drive circuit is given in Figure 10. PLC input/output assignments are given in Table 1. Input/output channels assignment for LabVIEW DAQboard are given in Table 2. System operation sequence is as follows:In order to initialize operation an external pushbutton is used. As a result of that solenoid valve (SV) is energized and cylinder out strokes. At the end of stroke the cylinder actuates limit switch (LS), which, enables an ON-Delay timer (T1). After the elapse of the timer preset time value the (SV) is deenergized and returns to its initial position. At this instance ON-Delay timer (T2) is enabled, up counter CTU is incremented, the timer T1 is disabled, and the solenoid valve is actuated again and the sequence repeats. The sequence is continued until the counter instantaneous count is equal to counter preset value and the sequence stops. For Siemens PLC (S7-214), the ladder diagram is shown in Figure 11, and the equivalentLabVIEW ladder diagram is shown in Figure 12. Experimental results show completely coincidence between both diagrams
7. Conclusions
Using LabVIEW environment, seven different timing virtual instruments have been designed and tested. Applying the same approach it is possible to design a complete set of PLC functions in order to realize able PC-based virtual PLC. In this case the virtual PLC will gain the advantages of PC-Based control.
REFERENCES
[1] M. K. Abuzalata, M. A. Alia, et al., “Designing Virtual PLC Using LabVIEW”, Applied Sciences Engineering and Technology, Maxwell Science Publication, UK, Vol.2, No. 3, 2010, p. 288.
[2] “Function and VI Reference Manual,” National Instruments,1998 Edition, Austin, USA.
[3] K. L. A. Shley, “Analog Electronics with LabVIEW,” Prentice Hall PTR, 2003.
[4] T. Mohioddin and M. Nawroki, “LabVIEW Advance Programming Techniques,” Second Edition, CRC Press, Boca Raton, 2006.
[5] J. Essick, “Hands-on Introduction to LabVIEW for Scientists and Engineers,” Oxford University Press, USA,2008.
[6] J. Y. Beyon, “Hands-on Exercise Manual for LabVIEW Programming, Data Acquisition and Analysis,” Prentice Hall PTR, USA, 2003.
[7] B. E. Paton, “Sensors, Transducers and LabVIEW,” Prentice Hall International (UK) Limited, London, 1993.
中文譯文
軟件工程與應(yīng)用,學(xué)報2011,4,172 - 180
開發(fā)與PLC功能和網(wǎng)絡(luò)等效的虛擬儀器
Mohammad A. K. Alia, Tariq M. Younes, Mohammad Abu Zalata
Received February 20th, 2011; revised March 5th, 2011; accepted March 10th, 2011.
摘要
本研究是對我們工作的一個延續(xù),發(fā)表在[1]。設(shè)計和測試了八個不同的時間VIs。這包括延遲打開、延遲斷開、單發(fā)射擊、可在觸發(fā)的單穩(wěn)態(tài)、累計計時器軟件。使用硬件可編程計數(shù)器/定時器芯片設(shè)計(DAQ-STC-24bit)和PCI MIO-16E-1 DAQ板兩個精確的計時器。在本文的結(jié)尾，開發(fā)一個電動氣動驅(qū)動系統(tǒng)和利用對延遲計時器控制設(shè)計VI功能，來解釋。實驗結(jié)果顯示基于plc程序控制和基于plc虛擬兩者之間的結(jié)果是一致的。
關(guān)鍵詞：可編程控制器，PLC虛擬，虛擬儀器，可編程定時器
1、 介紹
我們的工作“使用虛擬儀器設(shè)計虛擬PLC”，我們已經(jīng)表明我們可以創(chuàng)建代表的PLC功能和網(wǎng)絡(luò)的虛擬儀器?！∥覀儽容^基于PC和基于PLC的控制系統(tǒng),來得到兩個系統(tǒng)不斷在同一方向發(fā)展以取得更好的可編程性、連通性和連通接口。同時基于PC的DCSs是適合工業(yè)應(yīng)用的。他們是健大的和他們輕松地工作在一個開放的架構(gòu)模式,雖然PLC是配備特定的MMI軟件和偽標(biāo)準(zhǔn)變換軟件。我們表明,為了提高的可編程性PACs,我們幾乎把計算機的眾多優(yōu)點的PLC作為多任務(wù),無限的記憶,高速和可能創(chuàng)造出無限數(shù)量的可編程對象如計數(shù)器、計時器、移位寄存器和其他。因為之前的工作規(guī)模有限,我們不能覆蓋其他重要的工作，使用和模擬PLC功能。本文我們開發(fā)不同類型的使用虛擬儀器軟件[2]和NI DAQ板硬件的可編程定時器。虛擬儀器的基本功能,提供時間在毫秒級的“等待”和“等待多個“VIs。兩者都是基于相同的底層機制。大多數(shù)應(yīng)用程序工作的舒適,可用虛擬儀器測量,解決毫秒,更多的操作與第二分辨率[3 - 4]。一些應(yīng)用程序的需求和響應(yīng)時間毫秒級的決議,這是有問題的,主要是由于操作系統(tǒng),而不是一個虛擬儀器限制[5]。一些應(yīng)用程序的需求和響應(yīng)時間毫秒級的決議,這是有問題的,主要是由于操作系統(tǒng),而不是一個虛擬儀器限制[5]。如果應(yīng)用程序需要更高的精度和分辨率比內(nèi)置定時功能可以供應(yīng),那么你將不得不使用一些額外的硬件,比如我董事會或外部時鐘[6]。鎳板有兩個24位計數(shù)器芯片和一些船上的時鐘,可以算出精確定時(時間間隔)。與DAQ計數(shù)器定時器VIs、一個可以配置車載多功能硬件來完成各種任務(wù),包括精確定時,計數(shù)脈沖生成事件,和測量時間和頻率。產(chǎn)生一個脈沖計數(shù)器輸出當(dāng)預(yù)排程序的終端數(shù)(TC)是達到了。脈沖可以用于排序的目的。類似的基于硬件的時機可能是使用windows API函數(shù)進行“查詢性能計數(shù)器”。這個函數(shù)看起來在一個高分辨率的系統(tǒng)硬件計數(shù)器運行大約在1.2 MHz或0.8微秒數(shù)。實際的分辨率,一旦我們帳戶延期,調(diào)用該函數(shù),將大大減少,但仍遠比一個毫秒。關(guān)于實時操作系統(tǒng)(RTOS),它們被設(shè)計為運行一個程序非常精確定時。他們可以允許運行循環(huán)幾乎同樣的事情每個迭代(通常在微秒)。硬RTOSs時機可以執(zhí)行使用DAQ卡的內(nèi)部時鐘,給予更好的精度比軟件定時功能[7]。當(dāng)時,一些硬件平臺功能的FPGA,這可能是使用FPGA模塊編程虛擬儀器。NI ComactRIO和單板是例子。默認(rèn)的時鐘頻率的FPGA是40 MHz虛擬儀器。通用FPGA定時VIs[2]可能會生成一個時鐘周期。一次性脈沖或測量周期、脈沖寬度、積累期超過指定數(shù)量的脈沖和計數(shù)脈沖在指定的一段時間。然而FPGA VIs不包括準(zhǔn)備在延遲定時器,定時器和momostable延遲斷開可再觸發(fā)的計時器,找到廣泛應(yīng)用于PLC順序控制程序。建立在上面的,這個工作的目標(biāo)是說明設(shè)計不同類型的定時VIs使用虛擬儀器軟件為了被用作編程元素在虛擬PLC程序。
2、 接通延時時間
1）、接通延時-1
圖1顯示了前面板和程序框圖的組件軟件在延遲計時器。循環(huán)迭代顯示秒。由于循環(huán)迭代開始從零,增加功能被添加以啟動它在一個。因為等待圖標(biāo)有100毫秒的延遲每兩個迭代之間的10倍乘以定時器預(yù)先指定的值,為了測量時間延遲在秒。應(yīng)用程序的啟動信號后,它需要一些延遲時間間隔相等的功能有一個真正的狀態(tài)輸出。如果輸入信號是禁用的,定時器輸出立即改變低狀態(tài)。
2）接通延時-2
VI的組件顯示在框圖2。最初輸入信號不啟用和虛假的情況下被激活。選擇圖標(biāo)的輸出是0,即低于預(yù)設(shè)值,定時器的結(jié)果是輸出的計時器是關(guān)閉的。當(dāng)輸入信號是使真正的案件執(zhí)行,選擇圖標(biāo)將輸出值,來自輸出案例的結(jié)構(gòu)。迭代初始值的局部變量是零,那么它將增加所造成的延遲后等待圖標(biāo),然后由定時器預(yù)設(shè)值相比。當(dāng)比較函數(shù)的輸出是正確的,輸出的定時器就高。當(dāng)允許輸入信號就低,輸出的計時器同時就低。在這個VI,檢查案例的結(jié)構(gòu)是連續(xù)在一個掃描速率等于一毫秒,接受許多應(yīng)用程序。
（a）
（b）
（3）
在延遲定時器,(a)框圖;(b)面板(c)功能
3、關(guān)閉延時
1）關(guān)閉延時-1
前面板和方塊圖是圖3所示。當(dāng)循環(huán)和其他VI組件的位置在錯誤的情況下的情況下結(jié)構(gòu)。真實的案例有一個局部變量定時器的輸出,這是連接到選擇器終端。允許輸入的信號連接到選擇器終端的虛假情況。
2）關(guān)閉延時-2
給出了框圖如圖4。當(dāng)輸入是啟用的情況下被激活的真實和選擇圖標(biāo)將被選定為零。在這種情況下,輸出的比較函數(shù)是假和定時器輸出是正確的。當(dāng)輸入信號是禁用的虛假案件執(zhí)行,選擇圖標(biāo)被選中的值來自輸出案例的結(jié)構(gòu)。當(dāng)關(guān)閉延遲時間間隔過后比較函數(shù)的輸出是真的和定時器輸出是假的。
（a）
（b）
(a)真（b）假
4、單發(fā)定時器
和前面板的框圖如圖5所示。布爾指示器防止定時器輸出后再打開的推移預(yù)設(shè)值一次性計時器。在錯誤的情況下,輸出是關(guān)閉的,在比較時間定時器輸出使高。最后比較計時器再次低輸出。
5、可再觸發(fā)的單穩(wěn)態(tài)定時器VI
圖6顯示了框圖和前面板的計時器。當(dāng)允許輸入開關(guān),定時器輸出立即打開,計時器開始計時。一旦預(yù)定時間價值已經(jīng)運行,定時器輸出開關(guān)關(guān)閉,即使允許輸入仍在。每一個去在過渡的允許輸入重置計時器,即運行時間設(shè)置為預(yù)設(shè)值,定時器輸出接通。圖7顯示了一個三模延遲計時器。在延遲,延遲斷開和可再觸發(fā)的單穩(wěn)態(tài)計時器是建立在一個框圖,程序員可以選擇所需的定時器模式。
6、累計計時器vi
計時器框圖和前面板如圖8所示。添加函數(shù)的輸出和計時器預(yù)設(shè)值是連接到平等的比較函數(shù)。輸出相等的比較函數(shù)連接到一個終端的或門。的另一個輸入或門函數(shù)連接到反向輸入信號?；蚝瘮?shù)的輸出終端連接到有條件的while循環(huán)。
（a）
（b）
(c)
(a)框圖;(b)前面板;(c)功能
有條件的終端連接到一個終端的和門。其他輸入的與門連接到本地變量的輸入信號。與門的輸出是定時器輸出。while循環(huán)和上述組件是在真實情況下案例的結(jié)構(gòu)。當(dāng)輸入信號是不啟用虛假情況下被激活,那么局部變量的累積指
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