IntegratedCircuits集成電路電子信息類專業(yè)英語(yǔ)、計(jì)算機(jī)類專業(yè)英語(yǔ)文章

Integrated Circuits(集成電路) 英文原稿: The Integrated Circuit Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.They are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differing electrical properties can be accurately controlled by mixing the semiconductor with small amounts of other elements. This mixing is called doping. A semiconductor can be doped to contain more electrons (N-type) or fewer electrons (P-type). Examples of commonly used semiconductors are silicon and germanium. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively. A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common types of transistors, the bipolar-junction transistor (BJT) and the field-effect transistor (FET) are schematically illustrated in Figure 2.1.This figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P-N doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.The FET shown is an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. When a voltage is applied to the insulated gate terminal, a current is enabled to flow from the drain to the source. It is called N-channel, because the gate voltage induces an N-channel within the substrate, enabling current to flow between the N-regions. Another basic semiconductor structure is a diode, which is formed simply by a junction of N-type and P-type silicon. Diodes act like one-way valves by conducting current only from P to N. Special diodes can be created that emit light when a voltage is applied. Appropriately enough, these components are called light emitting diodes, or LEDs. These small lights are manufactured by the millions and are found in diverse applications from telephones to traffic lights. The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the out­side world.Small wires are connected within this package between the semiconductor sandwich and pins that protrude from the package to make electrical contact with other parts of the intended circuit. Once you have several discrete transistors, digital logic can be built by directly wiring these components together. The circuit will function, but any substantial amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates. At the time of the invention of the transistor in 1947 by John Bardeen, Walter Brattain, and William Shockley, the only way to assemble multiple transistors into a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a means of fabricating multiple transistors on a single slab of semiconductor material. Their invention would come to be known as the integrated circuit, or IC, which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors and diodes onto the same small semiconductor chip. Instead of having to solder individual wires between discrete components, an IC contains many small components that are already wired together in the desired topology to form a circuit. A typical IC, without its plastic or ceramic package, is a square or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used to manufacture the IC, there may be anywhere from a dozen to tens of millions of individual transistors on this small chip. This amazing density of electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in units of micrometers, with one micrometer (1mm) being one millionth of a meter. To serve as a reference point, a human hair is roughly 100mm in diameter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm! Each year, researchers and engineers have been finding new ways to steadily reduce these feature sizes to pack more transistors into the same silicon area, as indicated in Figure 2.2. When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes create BJTs, whereas MOS processes create FETs. Bipolar logic was more common before the 1980s, but MOS technologies have since accounted the great majority of digital logic ICs. N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, complementary-MOS, or CMOS, became the dominant process technology and remains so to this day. CMOS ICs incorporate both NMOS and PMOS transistors. Application Specific Integrated Circuit An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs. History The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies include RAM elements. Standard cell design In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost. By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis. *The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register transfer level) design. *Suitability for purpose is verified by simulation. A virtual system created in software, using a tool such as Virtutech’s Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second. *A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist. *The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement. *The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling semiconductor fabrication to produce physical ICs. *Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication. These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturer’s cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design. Gate array design Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.The physical design process then defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic blocks. Full-custom design The benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip. The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any performance limiting aspect of the design. Structured design Structured ASIC design is an ambiguous expression, with different meanings in different contexts. This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.One definition states that, in a structured ASIC design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Structured ASIC technology is seen as bridging the gap between field-programmable gate arrays and “standard-cell” ASIC designs. What makes a structured ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC the predefined metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well.Likewise, the design tools used for structured ASIC can substantially lower cost, and are easier to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. One other important aspect about structured ASIC is that it allows IP that is common to certain applications to be “built in”, rather than “designed in”. By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC. 中文翻譯： 集成電路 集成電路 數(shù)字邏輯和電子電路由稱為晶體管的電子開關(guān)得到它們的（各種）功能。粗略地說(shuō)，晶體管好似一種電子控制閥，由此加在閥一端的能量可以使能量在另外兩個(gè)連接端之間流動(dòng)。通過(guò)多個(gè)晶體管的組合就可以構(gòu)成數(shù)字邏輯模塊，如與門和觸發(fā)電路等。而晶體管是由半導(dǎo)體構(gòu)成的。查閱大學(xué)化學(xué)書中的元素周期表，你會(huì)查到半導(dǎo)體是介于金屬與非金屬之間的一類元素。它們之所以被叫做半導(dǎo)體是由于它們表現(xiàn)出來(lái)的性質(zhì)類似于金屬和非金屬。可使半導(dǎo)體像金屬那樣導(dǎo)電，或者像非金屬那樣絕緣。通過(guò)半導(dǎo)體和少量其它元素的混合可以精確地控制這些不同的電特性，這種混合技術(shù)稱之為“半導(dǎo)體摻雜”。半導(dǎo)體通過(guò)摻雜可以包含更多的電子（N型）或更少的電子（P型）。常用的半導(dǎo)體是硅和鍺，N型硅半導(dǎo)體摻入磷元素，而P型硅半導(dǎo)體摻入硼元素。 不同摻雜的半導(dǎo)體層形成的三明治狀?yuàn)A層結(jié)構(gòu)可以構(gòu)成一個(gè)晶體管，最常見(jiàn)的兩類晶體管是雙極型晶體管（BJT）和場(chǎng)效應(yīng)晶體管（FET），圖2.1給出了它們的圖示。圖中給出了這些晶體管的硅結(jié)構(gòu)，以及它們用于電路圖中的符號(hào)。BJT是NPN晶體管，因?yàn)橛蒒—P—N摻雜硅三層構(gòu)成。當(dāng)小電流注入基極時(shí)，可使較大的電流從集電極流向發(fā)射極。圖示的FET是N溝道的場(chǎng)效應(yīng)型晶體管，它由兩塊被P型基底分離的N型組成。將電壓加在絕緣的柵極上時(shí)，可使電流由漏極流向源極。它被叫做N溝道是因?yàn)闁艠O電壓誘導(dǎo)基底上的N通道，使電流能在兩個(gè)N區(qū)域之間流動(dòng)。 另一個(gè)基本的半導(dǎo)體結(jié)構(gòu)是二極管，由N型和P型硅連接而成的結(jié)組成。二極管的作用就像一個(gè)單向閥門，由于電流只能從P流向N。可以構(gòu)建一些特殊二極管，在加電壓時(shí)可以發(fā)光，這些器件非常合適地被叫做發(fā)光二極管或LED。這種小燈泡數(shù)以百萬(wàn)計(jì)地被制造出來(lái)，有各種各樣的應(yīng)用，從電話機(jī)到交通燈。 半導(dǎo)體材料上制作晶體管或二極管所形成的小芯片用塑料封裝以防損傷和被外界污染。在這封裝里一些短線連接半導(dǎo)體夾層和從封裝內(nèi)伸出的插腳以便與（使用該晶體管的）電路其余部分連接。一旦你有了一些分立的晶體管，直接用電線將這些器件連線在一起就可以構(gòu)建數(shù)字邏輯（電路）。電路會(huì)工作，但任何實(shí)質(zhì)性的數(shù)字邏輯（電路）都將十分龐大，因?yàn)橐诟鞣N邏輯門中每實(shí)現(xiàn)一種都需要多個(gè)晶體管。 1947年，John Bardeen、Walter Brattain和and William Shockley發(fā)明晶體管的時(shí)候。將多個(gè)晶體管組裝在一個(gè)電路上的唯一方法就是購(gòu)買多個(gè)分離的晶體管，將它們連在一起。1959年，Jack Kilby 和 Robert Noyce各自獨(dú)立地發(fā)明了一種將多個(gè)晶體管做在同一片半導(dǎo)體材料上的方法。這個(gè)發(fā)明就是集成電路，或IC，是我們現(xiàn)代電腦化世界的基礎(chǔ)。集成電路之所以被這樣命名，是因?yàn)樗鼘⒍鄠€(gè)晶體管和二極管集成到同一塊小的半導(dǎo)體芯片上。IC包含按照形成電路所要求的拓?fù)浣Y(jié)構(gòu)連在一起的許多小元件，而無(wú)需再將分立元件的導(dǎo)線焊接起來(lái)。 去除了塑料或陶瓷封裝后，一個(gè)典型的集成電路就是每一邊2mm至15mm的方形或矩形硅片。根據(jù)制造集成電路的技術(shù)水平的不同，在這種小片上可能有幾十個(gè)到幾百萬(wàn)個(gè)晶體管，電子器件這種令人驚異的密度表明那些晶體管以及連接它們線是極其微小的。集成電路的尺寸是以微米為單位測(cè)量的，1微米是1米的百萬(wàn)分之一。作為參照，一根人的頭發(fā)其直徑大約為100微米。一些現(xiàn)代集成電路包含的元件和連線，是以小到0.1微米的增量來(lái)測(cè)量的。每年研究人員和工程師都在尋找新的方法來(lái)不斷減小這些元件的大小，以便在同樣面積的硅片上集成更多的晶體管，如圖2.2所示。 在集成電路的設(shè)計(jì)和制造過(guò)程中，常用兩種主要晶體管技術(shù)是：雙極和金屬氧化物半導(dǎo)體（MOS）。雙極工藝生產(chǎn)出來(lái)的是BJT（雙極型晶體管），而MOS工藝生產(chǎn)出來(lái)的是FET（場(chǎng)效應(yīng)晶體管）。在20世紀(jì)80年代以前更常用的集成電路是雙極邏輯，但是此后MOS技術(shù)在數(shù)字邏輯集成電路中占據(jù)了大多數(shù)。N溝道FET是采用NMOS工藝生產(chǎn)的，而P溝道FET是采用PMOS工藝生產(chǎn)的。到了20世紀(jì)80年代，互補(bǔ)MOS即CMOS成為占主導(dǎo)地位的加工技術(shù)，并且延續(xù)至今。CMOS集成電路包含了NMOS和PMOS兩種晶體管。 專用集成電路（ASIC） 專用集成電路（ASIC）是為了特殊應(yīng)用而定制的集成電路，而不是通用的。比如，一片僅被設(shè)計(jì)用于運(yùn)行蜂窩式電話的芯片是專用集成電路（ASIC）。相比之下，7400與4000系列集成電路是可以用導(dǎo)線連接的邏輯構(gòu)建模塊，適用于各種不同的應(yīng)用。 隨著逐年來(lái)特征尺寸的縮小和設(shè)計(jì)工具的改進(jìn)，ASIC中的最大復(fù)雜度從5000個(gè)門電路增長(zhǎng)到了1億個(gè)門電路，因而功能也有極大的提高?，F(xiàn)代ASIC常包含32位處理器，包括ROM、RAM、EEPROM、Flash等存儲(chǔ)器，以及其它大規(guī)模組件。這樣的ASIC經(jīng)常被稱為SoC（片上系統(tǒng)）。數(shù)字ASIC的設(shè)計(jì)者們使用硬件描述語(yǔ)言（HDL），比如Verilog或VHDL語(yǔ)言來(lái)描述ASIC的功能。 現(xiàn)場(chǎng)可編程門陣列（FPGA）是7400系列和面包板的現(xiàn)代版，它包括可編程邏輯塊和可編程的模塊之間的相互連接，使得相同的FPGA能夠用于許多不同的場(chǎng)合。對(duì)于較小規(guī)模的設(shè)計(jì)或（與）小批量生產(chǎn)，F(xiàn)PGA可能比ASIC設(shè)計(jì)有更高的成本效率。不能循壞的工程費(fèi)用（建立工廠生產(chǎn)特定ASIC的成本）可能會(huì)達(dá)到數(shù)十萬(wàn)美元。 專用集成電路這一通用名詞也包括FPGA，但是大多數(shù)設(shè)計(jì)者僅將ASIC用于非現(xiàn)場(chǎng)可編程的器件，將ASIC和FPGA兩者區(qū)別開來(lái)。 歷史 最初的ASIC使用門陣列技術(shù)。Ferranti在1980年左右制作了也許是第一片門陣列，ULA（自由邏輯陣列）。通過(guò)改變金屬互相連接掩模產(chǎn)生了定制。ULA有多至幾千個(gè)門電路的復(fù)雜度。之后的版本變得更通用，有適應(yīng)用戶的包含金屬和多層硅的不同基底，有些基底包括RAM單元。 標(biāo)準(zhǔn)單元設(shè)計(jì) 在20世紀(jì)80年代中期，一個(gè)設(shè)計(jì)者要選擇一家ASIC制造商，并用制造商提供的設(shè)計(jì)工具完成他們的設(shè)計(jì)工作。盡管有第三方設(shè)計(jì)工具，但第三方設(shè)計(jì)工具和不同的ASIC制造商的布線以及實(shí)際半導(dǎo)體工藝過(guò)程的性能之間卻缺乏有效的聯(lián)系。大多數(shù)的設(shè)計(jì)者最終使用工廠特制的工具來(lái)完成他們的設(shè)計(jì)。解決這個(gè)問(wèn)題的一個(gè)方法是實(shí)現(xiàn)標(biāo)準(zhǔn)元件，這一問(wèn)題也帶來(lái)了更高密度的器件。每個(gè)ASIC制造商都可創(chuàng)造他們自己的具有已知電性能的功能塊，如傳播延遲器、電容、電感，這些都可以用第三方工具來(lái)表示（實(shí)現(xiàn)）。標(biāo)準(zhǔn)單元設(shè)計(jì)就是利用這些功能塊來(lái)實(shí)現(xiàn)很高的門密度以及良好的電性能。標(biāo)準(zhǔn)單元設(shè)計(jì)使門陣列和全定制設(shè)計(jì)之間在一次性投入的工程費(fèi)用和循環(huán)元件成本方面相互適應(yīng)。 直到80年代后期，邏輯綜合工具，比如設(shè)計(jì)編譯器，開始向廣大設(shè)計(jì)者提供。這些工具能夠?qū)DL描述語(yǔ)言編譯成門級(jí)的網(wǎng)表。這就使得稱作標(biāo)準(zhǔn)單元設(shè)計(jì)的設(shè)計(jì)方法成為可能。標(biāo)準(zhǔn)單元集成電路的設(shè)計(jì)過(guò)程在概念上需經(jīng)過(guò)以下幾個(gè)過(guò)程，但事實(shí)上在實(shí)際生產(chǎn)中這些工序都有較大的重疊。 以工業(yè)界普通的熟練水平實(shí)現(xiàn)的這些步驟幾乎總是產(chǎn)生能正確實(shí)現(xiàn)原設(shè)計(jì)的最終器件，除非后來(lái)在物理制造過(guò)程中引入了缺陷。 設(shè)計(jì)工程師團(tuán)隊(duì)開始工作于對(duì)新的ASIC所要求功能的非正式理解，這通常來(lái)自于需求分析。 *設(shè)計(jì)團(tuán)隊(duì)構(gòu)建對(duì)ASIC芯片的描述并使用HDL語(yǔ)言實(shí)現(xiàn)這些目標(biāo)。這一過(guò)程可類比于用高級(jí)語(yǔ)言編寫計(jì)算機(jī)程序。這一過(guò)程常被稱為RTL（寄存器傳送級(jí)）設(shè)計(jì)。 *仿真驗(yàn)證目標(biāo)的合適性。利用例如Virtutech’s Simics工具，用軟件構(gòu)建的虛擬系統(tǒng)能以高達(dá)每秒數(shù)十億條模擬指令的速度來(lái)模擬ASIC的功能。 *邏輯綜合工具，比如設(shè)計(jì)編譯器，將RTL設(shè)計(jì)轉(zhuǎn)換成稱為標(biāo)準(zhǔn)單元的較低層結(jié)構(gòu)的集合。這些構(gòu)成的元素是從一個(gè)標(biāo)準(zhǔn)單元庫(kù)中得到的，這個(gè)庫(kù)由事先規(guī)定好的門電路集合構(gòu)成，例如2輸入或非門，2輸入與非門，非門等等。有計(jì)劃的ASIC制造商有其特定的標(biāo)準(zhǔn)單元。所產(chǎn)生的所有標(biāo)準(zhǔn)單元，加上連接他們所需要的導(dǎo)線稱為門級(jí)網(wǎng)表。 *接著，門級(jí)網(wǎng)表由布局工具進(jìn)行處理，將標(biāo)準(zhǔn)單元布局在代表最終ASIC的區(qū)域。努力尋找一種標(biāo)準(zhǔn)單元的布局服從各種規(guī)定的約束。有時(shí)，先進(jìn)的技術(shù)比如模擬退火被用來(lái)優(yōu)化布局。 *路由工具獲取標(biāo)準(zhǔn)單元的物理布局，并利用網(wǎng)表來(lái)創(chuàng)建它們之間的電連接。由于搜索空間很大，該過(guò)程將產(chǎn)生滿足充分條件的解，而不是全局最優(yōu)解。這個(gè)過(guò)程的輸出是一套光掩模使半導(dǎo)體制造產(chǎn)生實(shí)物的IC。 *接下來(lái)是對(duì)最終延時(shí)、寄生電阻和電容以及能量消耗的周全的評(píng)估。對(duì)于數(shù)字電路，這將被進(jìn)一步對(duì)應(yīng)為延遲信息，這些評(píng)估將用于最后一輪的測(cè)試。這一測(cè)試表明器件將在所有極端的過(guò)程、電壓、溫度下正常工作。當(dāng)這項(xiàng)測(cè)試完成時(shí)，光掩模信息將被公布用于芯片制造。 這些設(shè)計(jì)步驟（或流程）對(duì)于標(biāo)準(zhǔn)產(chǎn)品設(shè)計(jì)同樣適用。重要的差別在于標(biāo)準(zhǔn)單元設(shè)計(jì)使用制造商的單元庫(kù)，這些庫(kù)已用于數(shù)以百計(jì)的其它設(shè)計(jì)實(shí)現(xiàn)，因而比起全定制設(shè)計(jì)來(lái)風(fēng)險(xiǎn)小得多。 門陣列設(shè)計(jì) 門陣列設(shè)計(jì)是一種制造方法，事先定義好擴(kuò)散層（晶體管和其它有源器件），包含這些器件的晶片在金屬化之前被庫(kù)存，就是說(shuō)先不進(jìn)行聯(lián)接。然后在物理設(shè)計(jì)過(guò)程中定義最終設(shè)計(jì)的連接。對(duì)設(shè)計(jì)者來(lái)說(shuō)重要的是，ASIC相比在市場(chǎng)上可提供的FPGA解決方案，能達(dá)到最小的傳播延時(shí)。門陣列ASIC是一種折中方案，因?yàn)閷⒛骋唤o定的設(shè)計(jì)與制造商庫(kù)存的晶片相對(duì)應(yīng)總是不可能達(dá)到100%利用率的。 現(xiàn)在電路設(shè)計(jì)者已經(jīng)很少采用純粹的邏輯門陣列設(shè)計(jì)，而幾乎都代之以FPGA之類的現(xiàn)場(chǎng)可編程器件了。這些器件可由用戶編程，使工具作業(yè)費(fèi)用最低，以略為提高的零件價(jià)格獲得可比的性能。現(xiàn)在門陣列正在發(fā)展為結(jié)構(gòu)化ASIC，其中包含很大的IP內(nèi)核，如處理器、DSP單元、外圍設(shè)備、標(biāo)準(zhǔn)接口、集成SRAM存儲(chǔ)器、以及一組可重新設(shè)置的未確定功能的邏輯單元。這種轉(zhuǎn)變很大程度上是因?yàn)锳SIC器件能夠集成大量的系統(tǒng)功能模塊，以及片上系統(tǒng)所要求的（功能）比僅僅邏輯單元多得多。 全定制設(shè)計(jì) 全