IntegratedCircuits集成電路電子信息類專業(yè)英語、計算機類專業(yè)英語文章

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1、Integrated Circuits(集成電路) 英文原稿: The Integrated Circuit Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection

2、of the valve enables energy to flow between two other connections.By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, an

3、d you will locate semiconductors as a group of elements separating the metals and nonmetals.They are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differi

4、ng electrical properties can be accurately controlled by mixing the semiconductor with small amounts of other elements. This mixing is called doping. A semiconductor can be doped to contain more electrons (N-type) or fewer electrons (P-type). Examples of commonly used semiconductors are silicon and

5、germanium. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively. A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common types of transistors, the bipolar-junction transistor (BJT) and the

6、field-effect transistor (FET) are schematically illustrated in Figure 2.1.This figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P

7、-N doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.The FET shown is an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. When a voltage is applied to the insulated gate

8、 terminal, a current is enabled to flow from the drain to the source. It is called N-channel, because the gate voltage induces an N-channel within the substrate, enabling current to flow between the N-regions. Another basic semiconductor structure is a diode, which is formed simply by a juncti

9、on of N-type and P-type silicon. Diodes act like one-way valves by conducting current only from P to N. Special diodes can be created that emit light when a voltage is applied. Appropriately enough, these components are called light emitting diodes, or LEDs. These small lights are manufactured by th

10、e millions and are found in diverse applications from telephones to traffic lights. The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the out-side world.

11、Small wires are connected within this package between the semiconductor sandwich and pins that protrude from the package to make electrical contact with other parts of the intended circuit. Once you have several discrete transistors, digital logic can be built by directly wiring these components tog

12、ether. The circuit will function, but any substantial amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates. At the time of the invention of the transistor in 1947 by John Bardeen, Walter Brattain, and William

13、 Shockley, the only way to assemble multiple transistors into a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a means of fabricating multiple transistors on a single slab of semiconductor material. Their in

14、vention would come to be known as the integrated circuit, or IC, which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors and diodes onto the same small semiconductor chip. Instead of having to solder individual wires between discrete co

15、mponents, an IC contains many small components that are already wired together in the desired topology to form a circuit. A typical IC, without its plastic or ceramic package, is a square or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used

16、to manufacture the IC, there may be anywhere from a dozen to tens of millions of individual transistors on this small chip. This amazing density of electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in un

17、its of micrometers, with one micrometer (1mm) being one millionth of a meter. To serve as a reference point, a human hair is roughly 100mm in diameter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm! Each year, researchers and engineers have been findi

18、ng new ways to steadily reduce these feature sizes to pack more transistors into the same silicon area, as indicated in Figure 2.2. When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes

19、create BJTs, whereas MOS processes create FETs. Bipolar logic was more common before the 1980s, but MOS technologies have since accounted the great majority of digital logic ICs. N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, comp

20、lementary-MOS, or CMOS, became the dominant process technology and remains so to this day. CMOS ICs incorporate both NMOS and PMOS transistors. Application Specific Integrated Circuit An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particul

21、ar use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications. As feature siz

22、es have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building b

23、locks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a bread

24、board, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. The non-recurring engineering cost (the cost to se

25、tup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs. History The in

26、itial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with dif

27、ferent base dies customized by both metal and polysilicon layers. Some base dies include RAM elements. Standard cell design In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design to

28、ols were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.Most designers ended up using factory specific tools to complete the implementation of their designs. A s

29、olution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in thir

30、d party tools.Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.

31、By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stage

32、s, although these stages overlap significantly in practice. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. A team of de

33、sign engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis. *The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-lev

34、el language. This is usually called the RTL (register transfer level) design. *Suitability for purpose is verified by simulation. A virtual system created in software, using a tool such as Virtutech’s Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions

35、per second. *A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input

36、 nand, inverters, etc.The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist. *The gate-level netlist is next processed by a placement tool

37、 which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement. *The routing tool takes the ph

38、ysical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling semiconductor fabrication to pr

39、oduce physical ICs. *Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrat

40、es that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication. These design steps (or flow) are also common to standard product design. The significant difference is tha

41、t Standard Cell design uses the manufacturer’s cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design. Gate array design Gate array design is a manufacturing method in which the diffused layers, i.e. transistors

42、 and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.The physical design process then defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be

43、 achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Pure, logic-only gate array design is rarely implemented by circuit designers today, repl

44、aced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.Today gate arrays are evolving into structured ASICs that consist of a large IP core like a pr

45、ocessor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic bloc

46、ks. Full-custom design The benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip. The disadvantages can include increased

47、manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performan

48、ce/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any performance limiting aspect of the design. Structured design Structured ASIC design is an ambiguous expression, with different meanings in different contexts.

49、This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers

50、 and pre-characterization of what is on the silicon.One definition states that, in a structured ASIC design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Structured ASIC technology is seen as bridging the gap between field-programmable gate

51、 arrays and “standard-cell” ASIC designs. What makes a structured ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC the predefined metallization is primarily to reduce cost of the mask sets and is

52、 also used to make the design cycle time significantly shorter as well.Likewise, the design tools used for structured ASIC can substantially lower cost, and are easier to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. One other impor

53、tant aspect about structured ASIC is that it allows IP that is common to certain applications to be “built in”, rather than “designed in”. By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC. 中文翻譯： 集成電路

54、 集成電路 數(shù)字邏輯和電子電路由稱為晶體管的電子開關得到它們的（各種）功能。粗略地說，晶體管好似一種電子控制閥，由此加在閥一端的能量可以使能量在另外兩個連接端之間流動。通過多個晶體管的組合就可以構成數(shù)字邏輯模塊，如與門和觸發(fā)電路等。而晶體管是由半導體構成的。查閱大學化學書中的元素周期表，你會查到半導體是介于金屬與非金屬之間的一類元素。它們之所以被叫做半導體是由于它們表現(xiàn)出來的性質類似于金屬和非金屬?？墒拱雽w像金屬那樣導電，或者像非金屬那樣絕緣。通過半導體和少量其它元素的混合可以精確地控制這些不同的電特性，這種混合技術稱之為“半導體摻雜”。半導體通過摻雜可以包含更多的電子（N型）或更少

55、的電子（P型）。常用的半導體是硅和鍺，N型硅半導體摻入磷元素，而P型硅半導體摻入硼元素。 不同摻雜的半導體層形成的三明治狀夾層結構可以構成一個晶體管，最常見的兩類晶體管是雙極型晶體管（BJT）和場效應晶體管（FET），圖2.1給出了它們的圖示。圖中給出了這些晶體管的硅結構，以及它們用于電路圖中的符號。BJT是NPN晶體管，因為由N—P—N摻雜硅三層構成。當小電流注入基極時，可使較大的電流從集電極流向發(fā)射極。圖示的FET是N溝道的場效應型晶體管，它由兩塊被P型基底分離的N型組成。將電壓加在絕緣的柵極上時，可使電流由漏極流向源極。它被叫做N溝道是因為柵極電壓誘導基底上的N通道，使電流能在兩個N區(qū)

56、域之間流動。 另一個基本的半導體結構是二極管，由N型和P型硅連接而成的結組成。二極管的作用就像一個單向閥門，由于電流只能從P流向N?？梢詷嫿ㄒ恍┨厥舛O管，在加電壓時可以發(fā)光，這些器件非常合適地被叫做發(fā)光二極管或LED。這種小燈泡數(shù)以百萬計地被制造出來，有各種各樣的應用，從電話機到交通燈。 半導體材料上制作晶體管或二極管所形成的小芯片用塑料封裝以防損傷和被外界污染。在這封裝里一些短線連接半導體夾層和從封裝內伸出的插腳以便與（使用該晶體管的）電路其余部分連接。一旦你有了一些分立的晶體管，直接用電線將這些器件連線在一起就可以構建數(shù)字邏輯（電路）。電路會工作，但任何實質性的數(shù)字邏輯（電路）都將十

57、分龐大，因為要在各種邏輯門中每實現(xiàn)一種都需要多個晶體管。 1947年，John Bardeen、Walter Brattain和and William Shockley發(fā)明晶體管的時候。將多個晶體管組裝在一個電路上的唯一方法就是購買多個分離的晶體管，將它們連在一起。1959年，Jack Kilby 和 Robert Noyce各自獨立地發(fā)明了一種將多個晶體管做在同一片半導體材料上的方法。這個發(fā)明就是集成電路，或IC，是我們現(xiàn)代電腦化世界的基礎。集成電路之所以被這樣命名，是因為它將多個晶體管和二極管集成到同一塊小的半導體芯片上。IC包含按照形成電路所要求的拓撲結構連在一起的許多小元件，而無需再

58、將分立元件的導線焊接起來。 去除了塑料或陶瓷封裝后，一個典型的集成電路就是每一邊2mm至15mm的方形或矩形硅片。根據(jù)制造集成電路的技術水平的不同，在這種小片上可能有幾十個到幾百萬個晶體管，電子器件這種令人驚異的密度表明那些晶體管以及連接它們線是極其微小的。集成電路的尺寸是以微米為單位測量的，1微米是1米的百萬分之一。作為參照，一根人的頭發(fā)其直徑大約為100微米。一些現(xiàn)代集成電路包含的元件和連線，是以小到0.1微米的增量來測量的。每年研究人員和工程師都在尋找新的方法來不斷減小這些元件的大小，以便在同樣面積的硅片上集成更多的晶體管，如圖2.2所示。 在集成電路的設計和制造過程中，常用兩種主要

59、晶體管技術是：雙極和金屬氧化物半導體（MOS）。雙極工藝生產出來的是BJT（雙極型晶體管），而MOS工藝生產出來的是FET（場效應晶體管）。在20世紀80年代以前更常用的集成電路是雙極邏輯，但是此后MOS技術在數(shù)字邏輯集成電路中占據(jù)了大多數(shù)。N溝道FET是采用NMOS工藝生產的，而P溝道FET是采用PMOS工藝生產的。到了20世紀80年代，互補MOS即CMOS成為占主導地位的加工技術，并且延續(xù)至今。CMOS集成電路包含了NMOS和PMOS兩種晶體管。 專用集成電路（ASIC） 專用集成電路（ASIC）是為了特殊應用而定制的集成電路，而不是通用的。比如，一片僅被設計用于運行蜂窩式電話

60、的芯片是專用集成電路（ASIC）。相比之下，7400與4000系列集成電路是可以用導線連接的邏輯構建模塊，適用于各種不同的應用。 隨著逐年來特征尺寸的縮小和設計工具的改進，ASIC中的最大復雜度從5000個門電路增長到了1億個門電路，因而功能也有極大的提高。現(xiàn)代ASIC常包含32位處理器，包括ROM、RAM、EEPROM、Flash等存儲器，以及其它大規(guī)模組件。這樣的ASIC經(jīng)常被稱為SoC（片上系統(tǒng)）。數(shù)字ASIC的設計者們使用硬件描述語言（HDL），比如Verilog或VHDL語言來描述ASIC的功能。 現(xiàn)場可編程門陣列（FPGA）是7400系列和面包板的現(xiàn)代版，它包括可編程邏輯塊和可

61、編程的模塊之間的相互連接，使得相同的FPGA能夠用于許多不同的場合。對于較小規(guī)模的設計或（與）小批量生產，F(xiàn)PGA可能比ASIC設計有更高的成本效率。不能循壞的工程費用（建立工廠生產特定ASIC的成本）可能會達到數(shù)十萬美元。 專用集成電路這一通用名詞也包括FPGA，但是大多數(shù)設計者僅將ASIC用于非現(xiàn)場可編程的器件，將ASIC和FPGA兩者區(qū)別開來。 歷史 最初的ASIC使用門陣列技術。Ferranti在1980年左右制作了也許是第一片門陣列，ULA（自由邏輯陣列）。通過改變金屬互相連接掩模產生了定制。ULA有多至幾千個門電路的復雜度。之后的版本變得更通用，有適應用戶的包含金屬和多層

62、硅的不同基底，有些基底包括RAM單元。 標準單元設計 在20世紀80年代中期，一個設計者要選擇一家ASIC制造商，并用制造商提供的設計工具完成他們的設計工作。盡管有第三方設計工具，但第三方設計工具和不同的ASIC制造商的布線以及實際半導體工藝過程的性能之間卻缺乏有效的聯(lián)系。大多數(shù)的設計者最終使用工廠特制的工具來完成他們的設計。解決這個問題的一個方法是實現(xiàn)標準元件，這一問題也帶來了更高密度的器件。每個ASIC制造商都可創(chuàng)造他們自己的具有已知電性能的功能塊，如傳播延遲器、電容、電感，這些都可以用第三方工具來表示（實現(xiàn)）。標準單元設計就是利用這些功能塊來實現(xiàn)很高的門密度以及良好的電性能。標準

63、單元設計使門陣列和全定制設計之間在一次性投入的工程費用和循環(huán)元件成本方面相互適應。 直到80年代后期，邏輯綜合工具，比如設計編譯器，開始向廣大設計者提供。這些工具能夠將HDL描述語言編譯成門級的網(wǎng)表。這就使得稱作標準單元設計的設計方法成為可能。標準單元集成電路的設計過程在概念上需經(jīng)過以下幾個過程，但事實上在實際生產中這些工序都有較大的重疊。 以工業(yè)界普通的熟練水平實現(xiàn)的這些步驟幾乎總是產生能正確實現(xiàn)原設計的最終器件，除非后來在物理制造過程中引入了缺陷。 設計工程師團隊開始工作于對新的ASIC所要求功能的非正式理解，這通常來自于需求分析。 *設計團隊構建對ASIC芯片的描述并使用HDL語

64、言實現(xiàn)這些目標。這一過程可類比于用高級語言編寫計算機程序。這一過程常被稱為RTL（寄存器傳送級）設計。 *仿真驗證目標的合適性。利用例如Virtutech’s Simics工具，用軟件構建的虛擬系統(tǒng)能以高達每秒數(shù)十億條模擬指令的速度來模擬ASIC的功能。 *邏輯綜合工具，比如設計編譯器，將RTL設計轉換成稱為標準單元的較低層結構的集合。這些構成的元素是從一個標準單元庫中得到的，這個庫由事先規(guī)定好的門電路集合構成，例如2輸入或非門，2輸入與非門，非門等等。有計劃的ASIC制造商有其特定的標準單元。所產生的所有標準單元，加上連接他們所需要的導線稱為門級網(wǎng)表。 *接著，門級網(wǎng)表由布局工具進行處

65、理，將標準單元布局在代表最終ASIC的區(qū)域。努力尋找一種標準單元的布局服從各種規(guī)定的約束。有時，先進的技術比如模擬退火被用來優(yōu)化布局。 *路由工具獲取標準單元的物理布局，并利用網(wǎng)表來創(chuàng)建它們之間的電連接。由于搜索空間很大，該過程將產生滿足充分條件的解，而不是全局最優(yōu)解。這個過程的輸出是一套光掩模使半導體制造產生實物的IC。 *接下來是對最終延時、寄生電阻和電容以及能量消耗的周全的評估。對于數(shù)字電路，這將被進一步對應為延遲信息，這些評估將用于最后一輪的測試。這一測試表明器件將在所有極端的過程、電壓、溫度下正常工作。當這項測試完成時，光掩模信息將被公布用于芯片制造。 這些設計步驟（或流程）對

66、于標準產品設計同樣適用。重要的差別在于標準單元設計使用制造商的單元庫，這些庫已用于數(shù)以百計的其它設計實現(xiàn)，因而比起全定制設計來風險小得多。 門陣列設計 門陣列設計是一種制造方法，事先定義好擴散層（晶體管和其它有源器件），包含這些器件的晶片在金屬化之前被庫存，就是說先不進行聯(lián)接。然后在物理設計過程中定義最終設計的連接。對設計者來說重要的是，ASIC相比在市場上可提供的FPGA解決方案，能達到最小的傳播延時。門陣列ASIC是一種折中方案，因為將某一給定的設計與制造商庫存的晶片相對應總是不可能達到100%利用率的。 現(xiàn)在電路設計者已經(jīng)很少采用純粹的邏輯門陣列設計，而幾乎都代之以FPGA之類的現(xiàn)場可編程器件了。這些器件可由用戶編程，使工具作業(yè)費用最低，以略為提高的零件價格獲得可比的性能。現(xiàn)在門陣列正在發(fā)展為結構化ASIC，其中包含很大的IP內核，如處理器、DSP單元、外圍設備、標準接口、集成SRAM存儲器、以及一組可重新設置的未確定功能的邏輯單元。這種轉變很大程度上是因為ASIC器件能夠集成大量的系統(tǒng)功能模塊，以及片上系統(tǒng)所要求的（功能）比僅僅邏輯單元多得多。 全定制設計 全