USB接口信號發(fā)生器

USB接口信號發(fā)生器,usb,接口,信號發(fā)生器 英文資料及中文翻譯 PDIUSBD12----USB interface device with parallel bus The PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer.This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments.This results in the fastest way to develop the most cost effective USB peripheral solution.The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed). It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices.Assuch, the PDIUSBD 12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations.The PDIUSBD12 low suspend power consumption along with the Lazy Clock output allowsfor easy implementation of equipment that is compliant to the ACPI(TM),OnNOW(TM), and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. In addition; it also incorporates features like SoftConnect(TM), GoodLink(TM), programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. 1. DMA transfer Direct Memory Address (DMA) allows an efficient transfer of a block of data between thehostandlocalsharedmemory.UsingaDMAcontroller, data transfer between the PDIUSBD12’s main endpoint (endpoint 2) and local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is set up for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive.This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation,the DMREQ pin will only be activated whenever the buffer is full, signalling that the host has successfully transferred a packet to the PDIUSBD12.With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput.When the host does not fill up the buffer completely (lessthan64 bytesor 128 bytes for single direction ISO configuration), the DMREQ pin will be deactivatedat the last byte of the buffer regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count. Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA writeoperation before the data is sent to the host. The only exception is at the end of DMA transfer, when the reception of pin EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfers, the local CPU and DMA controller have to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of pin DMACK_Nautomatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. Command description 2. Command procedure There are three basic types of commands: Initialization, Data Flow and General Commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. 2.1 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. ⑴ Set Address/Enable Code (Hex):D0 Transaction: write 1 byte This command is used to set the USB assigned address and enable the function. ⑵ Set endpoint enable Code (Hex):D8 Transaction: write 1 byte Thegeneric/Isochronous endpoints can only been abled when the function is enabled via the Set Address/Enable command. ⑶ Set mode Code (Hex):F3 Transaction: write 2 bytes The Set mode command is followed by two data writes. The first byte contains the configuration bits. The second byte is the clock division factor byte. ⑷ CLOCK DIVISION The value indicates the clock division factor for CLKOUT. The FACTOR output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up or down by the user. The minimum value is 1 giving the range of frequency from 4 to 24 MHz. The minimum value of N is 0, giving a maximum frequency of 48 MHz.The maximum value of N is 11 giving a minimum frequency of 4 MHz.The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. ⑸ Set DMA Code (Hex): FB Transaction: read/write 1 byte The set DMA command is followed by one data write/read to/from the DMA configuration register.DMA Configuration register: During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of this headers.For DMA read operations, the header will be skipped by the PDIUSBD12. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. 2.2 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data. ⑴ Read interrupt register Code (Hex):F4 Transaction: read 2 bytes This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers. ⑵ Select Endpoint Code (Hex):00 to 05 Transaction: read 1 byte (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte. FULL/EMPTY: A ‘1’ indicates the buffer is full, ‘0’ indicates an empty buffer. STALL: A ‘1’ indicates the selected endpoint is in the stall state. Fig 11. Select Endpoint command: bit allocation. ⑶ Read Endpoint status Code (Hex):80 to 85 Transaction: read 1 byte ⑷ Read last transaction status register Code (Hex):40 to 45 Transaction: read 1 byte The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read.This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction. ⑸ Read buffer Code (Hex):F0 Transaction: read multiple bytes (max. 130) The Read Buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1.The buffer pointer is not reset to the top of the buffer by the Read Buffer command.This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint). The data in the buffer are organized as follows: * byte 0: reserved; can have any value * byte 1: number/length of data bytes * byte 2: data byte 1 * byte 3: data byte 2 * etc. The first two bytes will be skipped in the DMA read operation. Thus, the first read will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. ⑹ Write buffer Code (Hex):F0 Transaction: write multiple bytes (max. 130) The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be ‘0’.During DMA writes operation, the first two bytes will be bypassed. Thus, the first write will write into Data byte 1, the second write will write into Data byte 2, etc. For non-isochronous transfer(bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host. Remark: There is no protection against writing or reading over a buffer’s boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation.Data in an OUT buffer are only meaningful after asuccessful transaction.The exception is during DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). ⑺ Clear buffer Code (Hex):F2 Transaction: none When a packet is received completely, an internal endpoint buffer full flag is set. All Subsequent packets will be refused by returning a NAK.When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the buffer is cleared, new packets will be accepted. ⑻ Validate buffer Code (Hex): FA Transaction: none When the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. ⑼ Set endpoint status Code (Hex):40 to 45 Transaction: write 1 byte A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it.When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.Even when unstalled, writing Set Endpoint Status to ‘0’ initializes the endpoint. 2.3 General commands Send resume Code (Hex)：F6 Transaction：none Sends an upstream resume signal for 10 ms.This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write. Read current frame number Code (Hex)：F5 Transaction：read 1 or 2 bytes This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant byte first. PDIUSBD12帶并行總線的USB接口器件 PDIUSBD12是一款性價比很高的USB器件，它通常用作微控制器系統(tǒng)中實現(xiàn)與微控制器進行通信的高速通用并行接口，它還支持本地的DMA傳輸。這種實現(xiàn)USB接口的標準組件使得設計者可以在各種不同類型微控制器中選擇出最合適的微控制器。這種靈活性減小了開發(fā)的時間，風險以及費用（通過使用已有的結構和減少固件上的投資），從而用最快捷的方法實現(xiàn)最經(jīng)濟的USB外設的解決方案。PDIUSBD12完全符合USB1.1版的規(guī)范，它還符合大多數(shù)器件的分類規(guī)格，成像類海量存儲器件，通信器件，打印設備以及人機接口設備。同樣地，PDIUSBD12理想地適用于許多外設。例如，打印機，掃描儀，外部的存儲設備（Zip驅動器）和數(shù)碼相機等等。它使得當前使用SCSI的系統(tǒng)可以立即降低成本。PDIUSBD12所具有的低掛起功耗連同LazyClock輸出可以滿足使用ACPI，OnNOW和USB電源管理的要求，低的操作功耗可以應用于使用總線供電的外設。此外它還集成了許多特性，包括SoftConnetTM，GoodLinkTM，可編程時鐘輸出，低頻晶振和終止寄存器集合。所有這些特性都為系統(tǒng)顯著節(jié)約了成本，同時使USB功能在外設上的應用變得容易。 1. DMA傳輸 直接存儲器尋址（DMA）允許在主端點和本地共享存儲器間實現(xiàn)數(shù)據(jù)塊的有效傳輸。使用DMA控制器，PDIUSBD12的主端點和本地共享存儲器間的數(shù)據(jù)傳輸可自主進行而不需要本地CPU的干預。要處理任何DMA傳輸，本地CPU從主機接收必要的SETUP信息并對 DMA控制器進行相應的編程，典型的對DMA控制器的傳輸模式，字節(jié)計數(shù)寄存器和地址計數(shù)器進行正確的編程。在該模式下，PDIUSBD12發(fā)出請求時開始傳輸。當字節(jié)計數(shù)器減少為零時終止。在DMA控制器編程之后，本地CPU在初始化傳輸時將PDIUSBD12中的DMA使能位置位。 PDIUSBD12可編程為單周期DMA或突發(fā)模式DMA。在單周期DMA中，DMREQ在每單個應答后直到被DMACK_N重新激活之前保持無效。在突發(fā)模式DMA中，DMREQ在器件中突發(fā)編程時一直保持有效。該過程持續(xù)到PDIUSBD12通過EOT_N接收到一個DMA終止信息。這時產(chǎn)生一個中斷指示本地CPU DMA操作已經(jīng)完成。 在DMA讀操作時DMREQ僅當緩沖區(qū)完全表示主機成功的發(fā)送了一個信息包到PDIUSBD12時才有效。由于具有雙緩沖配置，主機可以在第一個緩沖區(qū)被讀出時對第二個緩沖區(qū)進行填充，這種并行的處理有效的增加了數(shù)據(jù)吞吐量。當主機沒有完全填滿緩沖區(qū)的情況下（單向ISO配置時小于64或128字節(jié)），DMREQ會在緩沖區(qū)的最后一個字節(jié)時無效 而不管當前的DMA突發(fā)計數(shù)。在更新了DMA突發(fā)計數(shù)的下一個包發(fā)送時，DMREQ再次被激活。 DMA的寫操作與之相似，當緩沖區(qū)未裝滿時，DMREQ一直有效。當緩沖區(qū)填滿時，在下一個IN標志將信息包送入主機。當傳輸完成之后，DMREQ變?yōu)闊o效。同樣的，雙緩沖配置在這也改善了數(shù)據(jù)的吞吐量。在非同步傳輸中，批量模式和中斷。在數(shù)據(jù)被發(fā)送到主機之前，緩沖區(qū)需要通過DMA寫操作完全裝滿。唯一的例外是，在DMA傳輸結束時，EOT_N接收的信號將會停止DMA寫操作并且在下一個IN標志置位時將緩沖區(qū)的內(nèi)容傳送到主機。 在同步模式中，本地CPU和DMA控制器必須保證它們在一個USB幀（1ms）中能夠吞吐的最大信息包的規(guī)模。DMACK_N的激活將自動選擇主端點（端點2）而不管當前選擇的端點。PDIUSBD12的DMA操作可通過普通的I/O對其它端點的存取實現(xiàn)交叉存取。DMA操作可通過以下方式終止：復位DMA使能寄存器位或EOT_N加上DMACK_N以及 RD_N/WR_N的激活。 PDIUSBD12支持單地址模式中的DMA傳輸，也可以在DMA控制器的雙地址模式中工作。在單地址模式中DMA通過DREQ DMACK_N,EOT_N,WR_N和RD_N控制線實現(xiàn)傳輸。在雙地址模式中DMREQ,DMACK_N和EOT_N未用，取而代之的是CS_N,WR_N和RD_N控制信號。需要遵循PDIUSBD12的I/O模式傳輸協(xié)議。在讀周期中對DMAC信號源進行訪問，在寫周期對目標進行訪問，傳輸需要兩個單獨的總線周期來儲存暫存在DMAC中的數(shù)據(jù)。 2. 命令描述 有3種基本的類型的命令：初始化，數(shù)據(jù)流和通用命令。 2.1 初始化命令 初始化命令在USB網(wǎng)絡進行枚舉處理時使用，這些命令用于使能端點的功能，還可用來設置USB配的地址。 ⑴設置地址/使能 命令：D0h 處理：寫1字節(jié) 該命令用于設置USB分配的地址和使能功能。 地址 寫入的值即為地址 使能 置1使能該功能 ⑵設置端點使能 命令：D8h 處理：寫1字節(jié) 通過設置設置地址/使能命令后才可使能普通/同步端點 普通/同步 端點 值1表示普通/同步端點使能 ⑶設置模式 命令：F3h 處理：寫2字節(jié) 設置模式命令后跟2個寫入的數(shù)據(jù)，第一個字節(jié)包含配置字節(jié)信息，第二個字節(jié)是時鐘分頻因素字節(jié)。 配置字節(jié) 無LazyClock：1 表示CLKOUT不會切換到LazyClock，0表示CLKOUT在Suspend腳變高之后切換到LazyClock，LazyClock頻率是30KHz±40%，編程值將不過會被總線復位所改變。 時鐘運行：1表示內(nèi)部時鐘和PLL即使在掛起狀態(tài)下仍然運行，0表示只要不需要時，內(nèi)部時鐘晶振和PLL就停止運行，為了滿足嚴格的掛起電流要求，該位需要設置為0，已編程的值不會被總線復位所改變。 中斷模式：1表示報告所有的錯誤和“NAKing”并產(chǎn)生一個中斷。0表示只有OK被報告。編程值不會被總線復位所改變。 SoftConnect：1表示如果VBUS可用，上行數(shù)據(jù)上拉電阻就被連接，0表示不連接。已編程的值不會被總線復位所改變。 端點配置：該2位設置端點配置如下： 模式 0 非同步模式 模式 1 同步輸出模式 模式 2 同步輸入模式 模式 3 同步輸入/輸出模式 ⑷時鐘分頻系數(shù)字節(jié) 時鐘分頻系數(shù)：該值用來表示CLKOUT的時鐘分頻系數(shù)，用N表示分頻系數(shù)，那么輸出頻率就為48MHz/(N+1)，復位值為11。這產(chǎn)生4MHz的輸出頻率，然后可由用戶自行調(diào)節(jié)。當N為0時，得到最大頻率48MHz，當N取最大11時，得到最小頻率4MHz。PDIUSBD12的設計確保了在改變頻率時不會出現(xiàn)干擾，已編程的值不會被總線復位所改變。 SET_TO_ONE：該位需要在任何DMA讀或寫操作之前置為1。該位在上電復位值為0。復位后可將其一直設為1。 僅有SOF中斷模式：將該位置1后，僅當幀時鐘的起始（SOF）時刻引起中斷的產(chǎn)生 而不管引腳中斷模式的設置狀態(tài)設置（DMA位5） ⑸設置 DMA 命令：FBh 處理：讀/寫1字節(jié) 設置DMA命令后跟1個字節(jié)數(shù)據(jù)寫入/讀出 DMA配置寄存器 DMA配置寄存器 在DMA操作中，兩字節(jié)的緩沖區(qū)頭（狀態(tài)和字節(jié)長度信息）不參與傳送。這就允許了DMA數(shù)據(jù)的連續(xù)性，不插入信息頭。DMA讀操作時，信息頭被PDIUSBD12跳過，在DMA寫操作時，信息頭由PDIUSBD12自動添加，這就提供了一個簡潔的DMA數(shù)據(jù)傳輸。 DMA突發(fā)串：選擇DMA操作的突發(fā)串長度 00 單周期 DMA 01 突發(fā)串 4 周期 DMA 10 突發(fā)串 8 周期 DMA 11 突發(fā)串 16 周期 DMA DMA使能：向該位寫入1會通過激活DMREQ啟動DMA操作，在激活DMREQ之前需要裝滿（DMA讀操作）或清空（DMA寫操作）主端點緩沖區(qū)。在單周期DMA模式中，DMREQ在突發(fā)串數(shù)目耗盡后無效，然后下一個突發(fā)串時重新激活，這個過程一直持續(xù)到EOT_N和DMACK_N以及RD_N或WR_N一起被激活。此時將該位置0并終止DMA操作，DMA操作也可通過直接向該位寫入0來終止。 DMA方向：該位決定了DMA傳輸時數(shù)據(jù)流的方向，1表示從外部共享存儲器到PDIUSBD12（DMA寫操作），0表示從PDIUSBD12到外部共享存儲器（DMA讀操作）。 自動重裝：當該位設為1，DMA操作會自動重新啟動。 中斷腳模式：0表示正常的中斷腳模式，中斷寄存器所有位的邏輯或產(chǎn)生中斷，當該位寫入1時表示中斷會在USB總線上行數(shù)據(jù)流出現(xiàn)幀時鐘（SOF）起始位時產(chǎn)生中斷。其它中斷仍然有效。 端點索引4中斷使能：該位為1表示只要端點緩沖區(qū)包含一個有效的信息包就會產(chǎn)生中斷，通常在DMA操作時關閉以減少不必要的CPU響應。 端點索引5中斷使能：該位為1表示只要端點緩沖區(qū)有效，見緩沖區(qū)生效命令，就會產(chǎn)生中斷，通常在DMA操作時關閉以減少不必要的CPU響應。 2.2 數(shù)據(jù)流命令 數(shù)據(jù)流命令用于管理USB端點和外部微控制器之間的數(shù)據(jù)傳輸，通過微控制器中斷初始化大量的數(shù)據(jù)流。微控制器利用這些命令訪問和決定端點的FIFO是否含有有效的數(shù)據(jù)。 ⑴讀中斷寄存器 命令：F4h 處理：讀2字節(jié) 中斷寄存器字節(jié)1 中斷寄存器字節(jié) 2 該命令指示中斷的來源，通過讀端點最后處理狀態(tài)寄存器將端點中斷位（位0~5）清零，其它位在讀中斷寄存器后被清零。 總線復位：在總線復位后將產(chǎn)生一個中斷將該位置1?？偩€復位與通過RESET_N腳的硬件 復位基本相同，有一點除外，就是總線復位產(chǎn)生一個中斷并且器件在默認地址0處使能。 掛起改變：當PDIUSBD12沒有收到3個SOF時，將會進入掛起狀態(tài)并將掛起改變位置位。任何掛起或喚醒狀態(tài)的改變都會將該位置位并產(chǎn)生中斷。 DMA EOT：該位表示DMA操作已結束。 ⑵選擇端點 命令：00-05h 處理：可選讀1字節(jié) 選擇端點命令將內(nèi)部指針初始化到選擇的緩沖區(qū)起始位置?？蛇x的該命令可跟一個返回的讀出字節(jié)。 滿/空 1表示緩沖區(qū)已滿，0 表示緩沖區(qū)為空。 停止 1表示選擇的端點處于停止狀態(tài)。 ⑶讀端點狀態(tài) 命令：80-85h 處理：讀1字節(jié) ⑷讀最后處理狀態(tài)寄存器 命令：40-45h 處理：讀1字節(jié) 讀最后處理狀態(tài)寄存器命令后跟一個數(shù)據(jù)返回端點最后處理的狀態(tài)，該命令同時復位中斷寄存器中的相應位并將狀態(tài)清零表示已經(jīng)讀取，由于它保留了每次處理的記錄，所以該命令在以調(diào)試為目的時很有用。在每次新的處理之后會將原來的狀態(tài)信息覆蓋。 數(shù)據(jù)接收/發(fā)送成功：1表示數(shù)據(jù)已經(jīng)成功地接收或發(fā)送。 SETUP信息包：1表示最后成功接收的信息包有一個SETUP標志，對IN緩沖區(qū)進行讀總為0。 數(shù)據(jù)0/1包：1表示最后成功接收/發(fā)送包含有一個DATA1 PID。 前一狀態(tài)未讀：1表示在前一狀態(tài)被讀出之前發(fā)生了第二個事件。 ⑸讀緩沖區(qū) 命令：F0h 處理：讀多個字節(jié)，最大130 讀緩沖區(qū)命令后，返回一系列從選擇的端點數(shù)據(jù)緩沖區(qū)讀出的數(shù)據(jù)，每讀一個字節(jié)，內(nèi)部緩沖區(qū)指針自動加一，讀緩沖區(qū)命令不會將緩沖區(qū)指針復位到緩沖區(qū)起始端，這意味著可被其它的命令所中斷（選擇端點命令除外）。 緩沖區(qū)數(shù)據(jù)結構如下 字節(jié)1：保留;可為任意值 字節(jié)2：數(shù)據(jù)字節(jié)的數(shù)目/長度 字節(jié)3：數(shù)據(jù)字節(jié)1 字節(jié)4：數(shù)據(jù)字節(jié)2 …… 頭兩個字節(jié)在DMA讀操作中可跳過。因此第一個讀出的字節(jié)是數(shù)據(jù)字節(jié)1。第二個讀出的是數(shù)據(jù)字節(jié)2等等。PDIUSBD12可通過USB信息包的EOP終止來決定包的最后一個字節(jié)。 ⑹寫緩沖區(qū) 命令：F0h 處理：寫多個字節(jié)，最大130 寫緩沖區(qū)命令后跟一系列需要寫入端點緩沖區(qū)的數(shù)據(jù)，數(shù)據(jù)的結構必須與前面描述的讀緩沖區(qū)命令一樣。第一個字節(jié)（保留）總為0。在DMA寫操作中，頭兩個字節(jié)會被繞過，因此，第一個寫入的字節(jié)是數(shù)據(jù)字節(jié)1。第二個寫入的是數(shù)據(jù)字節(jié)2等等。在非同步傳輸（批量或中斷）中，數(shù)據(jù)被發(fā)送到主機之前緩沖區(qū)必須被完全填滿并切換到下一個緩沖區(qū)。例外的情況是，當前的緩沖區(qū)內(nèi)容將要被發(fā)送到主機時，由有效的EOT_N指示DMA傳輸?shù)慕Y束。 ⑺清緩沖區(qū) 命令：F2h 處理：無 當一個信息包完全接收之后，內(nèi)部端點緩沖區(qū)滿標志置位，所有后續(xù)的包將被返回的NAK拒絕，當微控制器已讀取數(shù)據(jù)，它應當通過清緩沖區(qū)命令來釋放緩沖區(qū)，當緩沖區(qū)清空之后新的信息包就可被接受了。 ⑻使緩沖區(qū)有效 命令：Fah 處理：無 當微控制器已將數(shù)據(jù)寫入IN緩沖區(qū)，它應當通過使緩沖區(qū)有效命令設置緩沖區(qū)滿標志，這表示緩沖區(qū)內(nèi)的數(shù)據(jù)有效并可在接收到下一個IN標志時將其送入主機。 ⑼設置端點狀態(tài) 命令：40-45h 處理：寫1字節(jié) 當一個停止控制的端點接收到SETUP標志時自動解除停止，而不管信息包的內(nèi)容如何，如果端點應當停在停止狀態(tài)，微控制器可以重新停止它。 當一個停止的端點解除了停止，設置端點命令或接收到一個SETUP標志，它同時被重新初始化將緩沖區(qū)刷新，如果是OUT緩沖區(qū)就等待一個DATA 0 PID，如果是IN緩沖區(qū)就寫入一個DATA 0 PID，即使在解除停止時，將設置端點狀態(tài)寫為0，也將初始化端點。 停止 1 表示端點處于停止狀態(tài) 2.3普通命令 發(fā)送恢復 命令：F6h 處理：無 發(fā)送一個上行數(shù)據(jù)流恢復信號10ms，該命令通常用于器件處于掛起狀態(tài)時，恢復命令后不跟讀出或寫入的數(shù)據(jù) 讀當前幀數(shù)目 該命令后跟1到2個讀出的字節(jié)并返回最后成功接收的SOF幀數(shù)目，幀數(shù)目為返回的低位字節(jié)。 12