裝配圖大學生方程式賽車設計（總體設計）（有cad圖+三維圖）

裝配圖大學生方程式賽車設計（總體設計）（有cad圖+三維圖）,裝配,大學生,方程式賽車,設計,總體,整體,cad,三維 IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B VOL 18 NO I FEBRUARY 1995 Electrical Characterization of the Interconnected Mesh Power System IMPS MCM Topology L W Schaper Member IEEE S Ang Member IEEE Yee L Low and Danny R Oldham Abstract A simcant decrease in MCM substrate production cost can be achieved by reducing the number of substrate layers from the conventional four or five power ground X signal Y signal pad to two or three Besides reducing direct processing steps yield will also increase as defect producing operations are eliminated This paper describes the Interconnected Mesh Power System IMPS a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution and dense signal interconnection on only two metal layers Several possible implementations of the topology in MCM D and MCM L are described The design of a test vehicle which characterizes both the signal transmission and power distribution properties of the IMPS topology is discussed The test vehicle has been built in an aluminumlpolyimide on silicon process developed at DEC Results of signal transrmss ion measurements impedance delay and crosstalk for various sigoavpOwer ground configurations are presented Power distribution characteristia de drops and ac noise are presented and compared with measurements on a test vehicle implemented with solid power and ground planes From the measured characteristics of the test vehicle the applicability clock frequency power etc for the IMPS topology has been determined Most MCM applications can benefit from the substrate cost reduction enabled by IMPS Indew rem Mdtichip modules cost reduction power distri bution decoupling interdigitated mesh planes I INTRODUCTION ESIDES producing MCM substrates in large panel for B mat to achieve economies of scale the surest way to achieve substrate cost reduction is to reduce the number of manufacturing process steps Though material cost reduction and process tweaking can have some impact more substantial cost reduction can be obtained by eliminating substrate layers Although some simple MCM s have been made with one or two metal layers almost all MCM D implementations have used four or five power plane ground plane X signal Y signal and perhaps a pad layer This topology is a natural extension of printed wiring board construction Unfortunately for most MCM D s every metal layer costs approximately the same no matter if it is a solid plane or a wiring layer with Manuscript received February 1994 revised July 13 1994 This work is supported by the Advanced Research Projects Agency under Grant MDA972 93 1 0036 This paper was presented at the 44th Electronic Components and Technology Conference Washington DC May 4 1994 The authors are with the High Density Electronics Center HiDEC University of Arkansas Fayetteville AR 72701 USA IEEE Log Number 9407917 x Y via Y Y Ground Grynd Pov la 99 b Fig 1 Derivation of the IMPS topology 300 cdcm2 of wiring capability this is due to deposition and lithography techniques employed Moreover the capabilities of batch via production methods have not heretofore been used to advantage in MCM D and some MCM L compared with the sequentially drilled vias of wiring boards 11 THE IMPS TOPOLOGY The Interconnected Mesh Power System IMPS is a new systematic topology which allows low inductance planar power and ground distribution as well as dense controlled impedance low crosstalk signal transmission in only two physical wiring layers It utilizes the production methods of fine line lithography and batch via fabrication characteristic of MCM D and some MCM L to create a structure not economically possible using standard printed wiring board methods The derivation of the power distribution structure is shown sequentially in Fig 1 Consider a familiar meshed plane used in many MCM s for power or ground Think of this construction not as a plane with holes however but as a set of X and Y conductors In Fig l a the X conductors and Y conductors have been placed on two separate metal layers and at each crossover a via has been provided to retain the planar characteristics Vias typically have low resistance and inductance compared with lines This interconnected mesh 1070 9894 95 04 000 1995 IEEE 100 IEEE TRANSACTIONS ON COMPONENTS PA Signal Signal Fig 2 Sparse IMPS implementation ZKAGING AND MANUFACTURING TECHNOLOGY PART B VOL 18 NO 1 FEBA p Grid Ground Grid plane is reasonably electrically equivalent to but topologically different from the conventional mesh plane The mesh of Fig l a includes enough space between con ductors to insert interdigitated conductors of opposite polarity power or ground with their own set of interconnecting vias on the same two physical metal layers Fig l b The resulting interconnecied mesh structure forms a complete power distribution system with the necessary characteristics of low resistance and inductance In this dense mesh of power and ground conductors there is no room for signals Yet if every other power and ground conductor and the corresponding vias were omitted the resulting sparse power distribution mesh structure would still be planar but containing less metal would be more resistive and inductive Signal wiring at an average spacing twice that of minimum conductor pitch could be provided as in Fig 2 However this arrangement results in adjacent signal tracks with potentially high crosstalk and poor impedance control Many variations of a fine i e minimum design rule interconnected mesh are possible with signal conductors sub stituting for up to almost half of the power and ground conductors but always keeping at least one power or ground conductor between adjacent signal conductors An ongoing tradeoff between available signal line density and power distribution integrity results and care must be taken not to disconnect portions of a power or ground plane The following wire sequences indicate several possibilities with the nP figure denoting average signal line pitch as a multiple of minimum wire pitch GSGPGPSPGPGSG 5P GSGPSPGSGPSP 3P GSGSGPSPSPGS 2 5P GSGSGSGSGSGS 2P NO The last sequence could potentially disconnect or at least non planarize the power plane A better solution is to adopt a coarse i e non minimum design rule mesh for power distribution For example in an MCM D technology with 20 pm minimum line and space a design rule of 100 pm line and 60 pm space could be adopted for the power wiring Power or ground conductors on 320 pm pitch are shown in Fig 3 Signal wiring in areas not requiring very high density would be inserted 20 pm wide Fig 3 Cl LUARY 1995 Fig 4 density a Signal lines between power and ground b Signal lines at high conductor into the 60 pm space between power and ground conductors 160 pm signal wire pitch Fig 4 a In areas where greater signal wire density might be required signal wires could be dropped into power or ground conductors Fig 4 b with a resulting signal line pitch of 80 pm Note that the split power or ground conductor uses four signal sized vias to replace the large power vias at the appropriate crossovers to maintain mesh continuity The implications of these geometries on signal propagation characteristics will be discussed later The 80 pm signal line pitch compares well SCHAPER et al ELECTRICAL CHARACTERIZATION OF THE INTERCONNECTED MESH POWER SYSTEMS IMPS MCM TOPOLOGY 101 BGA fl Pads Fig 5 IMPS on film carrier with the 75 pm pitch 25 pm line and 50 pm space used on many conventional MCM signal layers to reduce crosstalk The IMPS topology offers far greater crosstalk reduction by interposing an ac ground conductor between every pair of signal conductors III IMPS TOPOLOGY IMPLEMENTATIONS The IMPS topology is easily implemented in a conventional MCM D process where fine line lithography and batch fine via fabrication are intrinsic to normal manufacturing An MCM L implementation is quite practical if via fabrication is by other than normal mechanical drilling and via size is small enough not to impact line pitch A two layer process however opens up the possibility of fabricating conductors on either side of a piece of poly mer film which could be processed in reel to reel format Fig 5 a The resulting substrate could be populated and tested then encapsulation applied to form a rigid structure Fig 5 b Inexpensive screen printing materials and meth ods could be used to form a ball grid array BGA on the bottom of the module providing a convenient system interface Fig 5 c Modules of this kind could be extremely inexpensive yet still yield high performance Iv IMPS ANALYSIS AND EXPERIMENT Because the IMPS topology is radically different from the conventional microstrip or stripline MCM transmission line environment with solid power and ground planes a detailed study to determine the characteristics of the power and signal environments was undertaken A Power Distribution Normal MCM power distribution is by solid metal power and ground planes sometimes with an intervening thin di electric which creates a parallel plate decoupling capacitor to supply all or part of transient current demands In most cases however surface mounted ceramic capacitors are needed as charge reservoirs to keep transient di dt noise on these planes below acceptable margins Conventional chip capacitors have relatively high parasitic inductance and low resonant frequency however Special low inductance capacitors made by AVX originally designed for the IBM Thermal Conduction Module provide far better decoupling The parallel plate P G planes themselves form a low inductance distribution structure Wirebonds from these planes to the chips even though many are paralleled contribute far more inductance and can critically affect on chip noise The IMPS topology replaces solid planes with a mesh of conductors In a dual mesh plane of 100 pm wide conductors on 320 pm pitch net metal coverage is reduced to 62 that of a solid plane Even with substantial power and ground conductor cuts to accommodate signal wires metal coverage of 40 can be realized Increased resistive and inductive parasitics are thus expected However since the contribution of these parasitics to dc and ac drops in the solid plane case is I02 IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART 8 VOL 18 NO 1 FEBRUARY 1995 111 Fig 6 Test vehicle power transient measurement setup often insignificant this performance decrease is manageable in almost all cases Attachment of both normal and low inductance decoupling capacitors in the conventional manner provides the necessary decoupling capacitance over a wide frequency range To examine the effectiveness of IMPS power distribution two test vehicles were designed and built one with solid planes the other with IMPS On each four n channel power FET s are arranged to connect on module resistive loads between power and ground thus inducing large di dt into the power distribution structure As shown in Fig 6 several sites are provided for normal ceramic as well as low inductance chip capacitors For clarity other features of the test vehicle for signal transmission measurements have not been shown Various combinations of capacitors and loads as well as current rise times were tried Resulting measurements are described later B Signal Transmission The IMPS signal transmission environment is shown in Fig 7 Each signal conductor lies between ac ground con ductors on the same metal plane and over orthogonal power ground and signal conductors on the other metal plane Because the ac ground conductors in the second plane are orthogonal to the signal line of interest return currents flow only in the coplanar conductors the orthogonal conductors moderately reduce the line impedance through capacitive loading This was initially demonstrated by building large scale physical models 160 times the size of MCM dimensions and doing TDR measurements and has been confirmed by measurements on the IMPS test vehicle described below C Test Vehicle The test vehicle shown in Fig 8 was designed and fabricated in a HiDEC developed four mask process using aluminum conductors and photodefinable polyimide dielectric on 5 sil icon substrates The fabrication process began with 2 pm of Fig 7 IMPS signal transmission environment Si02 deposited by PECVD on bare Si wafers or an 8 pm layer of DuPont 2721 polyimide Next 2 pm of AVl Si was sputtered and defined by photolithography and wet etching Next a layer of polyimide was spun on exposed and devel oped Mask features of 50 pm for large power vias and 15 pm for signal and small power vias were used The metal deposition and patterning was repeated to form the second metal layer and a final polyimide step formed a protective overcoat Several thicknesses of interlayer and base layer dielectric were compared The 33 x 26 mm substrate was populated with decoupling capacitors and terminating resistors and was used unpack aged for transmission line and power distribution impedance measurements or it received power FET chips decoupling capacitors and load resistors and was mounted in a 256 lead CQFP package for measurements of dc drop and ac power distribution noise The solid plane version used for power distribution measurements was likewise configured Both substrates were fabricated using the same four masks with the IMPS substrate occupying six of the eight possible 5 wafer sites and the solid plane substrate the remaining two sites D Signal Transmission Structures and Measurement Results Several different signal transmission test structures have been included in the IMPS test vehicle All have microwave probe pads on 150 pm pitch at either end and provision to terminate the line using a 50 R 0603 size 1 6 x 0 8 mm chip resistor bonded to the substrate with conductive epoxy For all transmission line measurements decoupling capacitors sufficient to hold the power distribution impedance below 0 5 R from 1 MHz to 1 GHz were installed See the following section on power distribution impedance Second level metal lines either 24 6 mm or 26 6 mm long were configured as signal between power and ground conductors PSG signal inside a split power conductor PSP and signal inside a split ground conductor GSG There is also a crosstalk measurement set of lines on 80 pm pitch the driven line lying between power and ground and the victim line within the adjacent split ground conductor First level lines lying on the Si02 or polyimide dielectric 18 2 mm long configured as PSP GSG and PSG were also measured to see if line impedance differed from second metal One aspect of the IMPS topology raised particular concern This was the effect on impedance and particularly on prop agation velocity of changing from for example an X going SCHAPER et al ELECTRICAL CHARACTERIZATION OF THE INTERCONNECTED MESH POWER SYSTEMS IMPS MCM TOPOLOGY 0 10 1 Fig 8 IMPS test vehicle PSP line to a Y going GSG line There is a discontinuity at the point of return current path change which has some effect depending on how well P and G are decoupled at frequencies of interest This has not appeared to be a problem in many MCM s where signal layers are routinely referenced either to power or ground planes with no effect To determine if a problem exists in IMPS a five segment path was created with 2 4 mm PSP 6 3 mm GSG 11 5 mm PSP 6 3 mm GSG and 2 4 mm PSP sections in series Substrates with an interlevel and overcoat polyimide thick ness of 4 0 pm and initial Si02 dielectric thickness of 2 pm were built and measured Measurements were performed using a Tektronix IPA 310 Interconnect Parameter Analyzer The results are shown below Z the M1 figures were higher due to the proximity of the substrate No problems were caused 103 by signals being referenced to power or ground the delay of the five segment line was no different from the other M2 lines The mask set was revised and the experiment was repeated with 8 pm thick polyimide for the initial dielectric layer and 5 4 pm of polyimide between M1 and M2 The following results were obtained ZoR t ps cm M1 PSP 42 72 M1 GSG 42 72 M1 PSG 42 70 M2 PSP 52 66 M2GSG 52 66 M2PSG 52 66 M2 5 Seg 52 68 Even with an 8 pm layer of polyimide the semiconducting silicon still has an effect As we are currently using test wafers as substrates the wafer resistivity is not known Further fabrication will use measured resistivity wafers to determine the resistivity necessary to eliminate the difference between M1 and M2 transmission lines Detailed simulations of lines above semiconducting substrates are also in progress Of course a different implementation of the topology on an insulating substrate of low dielectric constant would not have this problem The crosstalk measurement was made on M2 lines with 28 5 mm coupled length Both ends of the victim line were terminated Measurements were made on the IPA 310 by injecting the 20 pS rise time TDR pulse into the driven line and measuring the victim line Peak crosstalk was less than 3 6 on this set of long coupled lines This result indicates 104 IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B VOL 18 NO 1 FEBRUARY 1995 m c 12 1 0 0 100 200 300 400 500 Frequency MHz Millions Fig IO impedance meter Power distribution impedance versus frequency using the HP 4291A that crosstalk should not be a problem at reasonable clock frequencies and line lengths E Power Distribution Impedance Measurements Power distribution impedance was measured using both an HP 8510 Network Analyzer and an HP 4291A Impedance Meter A range of 45 MHz to 1 GHz could be measured with the 8510 Fig 9 shows the measured impedance for several substrates with various combinations of decoupling capacitance The effect of even the low inductance AVX capacitors only appears below 300 MHz above this frequency the intrinsic capacitance of the planes in either solid 3 2 nF or IMPS 1 6 nF versions dominates the measured impedance The rising impedance from 600 to 900 MHz is due to inductive effects With the 4291A measurements were made from 1 to 500 MHz as shown in Fig 10 The resonance of the 0 1 pF chip capacitors is clearly seen around 20 MHz These measurements were made without AVX capacitors in place in order to confirm the SPICE models which predict the rise in impedance with the normal caps in place between 200 and 300 MHz The results indicate that there is little difference between the IMPS power distribution structure and one using solid planes Any planar effects will be masked by attachment or wirebonding impedances and by the number and type of capacitors used The procedure used to attach chip capacitors is extremely important as the aluminum lines of the substrate form native aluminum oxide rapidly and even this roughly 80 A of oxide can produce measurable resistances in power paths This may account for the inability to achieve extremely low impedances F Power Distribution DC and AC Measurements The test vehicle shown in Fig 6 was built in both IMPS and solid plane designs Each was assembled with two 0 1 pF chip capacitors and four 135 nF AVX capacitors for decoupling Six paralleled 50 R resistors were used as loads 8 3 R resistance for each of the four power FET s The substrates were assembled into 256 lead CQFP packages with 110 ground and 80 power connections to ensure solid power distribution to the substrate These packages were soldered to custom well decoupled test boards The resulting assemblies were measured for dc voltage drops with large currents flowing through the load resistors and for ac noise on the substrate planes with large dI dt induced by driving the FET gates with a pulse generator Because of assembly problems only three of the four FET load sections could be activated and some load resistors were inoperative so the effective resistance of these test vehicles was 3 9 R However this was sufficiently low that ample current could be drawn even with the 10 V m